Lines Matching refs:i2c_dev

144 static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev)
146 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
151 static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
156 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
157 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
159 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
167 dev_err(i2c_dev->dev,
179 dev_err(i2c_dev->dev,
186 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
191 static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
193 u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
216 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD)
222 i2c_dev->base + STM32F4_I2C_TRISE);
225 static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
230 if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
246 val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2);
266 val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3);
273 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR);
278 * @i2c_dev: Controller's private data
280 static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev)
284 ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev);
288 stm32f4_i2c_set_rise_time(i2c_dev);
290 stm32f4_i2c_set_speed_mode(i2c_dev);
293 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1);
298 static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev)
303 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2,
308 dev_dbg(i2c_dev->dev, "bus not free\n");
317 * @i2c_dev: Controller's private data
320 static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte)
322 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR);
327 * @i2c_dev: Controller's private data
331 static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev)
333 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
335 stm32f4_i2c_write_byte(i2c_dev, *msg->buf++);
339 static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev)
341 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
344 rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR);
349 static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev)
351 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
354 stm32f4_i2c_disable_irq(i2c_dev);
356 reg = i2c_dev->base + STM32F4_I2C_CR1;
362 complete(&i2c_dev->complete);
367 * @i2c_dev: Controller's private data
369 static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev)
371 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
372 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
375 stm32f4_i2c_write_msg(i2c_dev);
384 stm32f4_i2c_terminate_xfer(i2c_dev);
390 * @i2c_dev: Controller's private data
394 static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev)
396 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
397 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
401 stm32f4_i2c_disable_irq(i2c_dev);
402 stm32f4_i2c_read_msg(i2c_dev);
403 complete(&i2c_dev->complete);
422 stm32f4_i2c_read_msg(i2c_dev);
429 * @i2c_dev: Controller's private data
434 static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
436 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
451 reg = i2c_dev->base + STM32F4_I2C_CR1;
458 stm32f4_i2c_read_msg(i2c_dev);
460 reg = i2c_dev->base + STM32F4_I2C_CR2;
464 complete(&i2c_dev->complete);
472 reg = i2c_dev->base + STM32F4_I2C_CR1;
474 stm32f4_i2c_read_msg(i2c_dev);
477 stm32f4_i2c_read_msg(i2c_dev);
484 * @i2c_dev: Controller's private data
486 static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev)
488 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
493 stm32f4_i2c_terminate_xfer(i2c_dev);
496 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
506 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
508 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
510 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
516 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
526 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
529 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
531 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
541 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
544 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
546 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
558 struct stm32f4_i2c_dev *i2c_dev = data;
559 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
563 cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2);
570 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
573 dev_dbg(i2c_dev->dev,
581 stm32f4_i2c_write_byte(i2c_dev, msg->addr);
586 stm32f4_i2c_handle_rx_addr(i2c_dev);
588 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
595 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
600 stm32f4_i2c_handle_write(i2c_dev);
604 stm32f4_i2c_handle_read(i2c_dev);
615 stm32f4_i2c_handle_rx_done(i2c_dev);
617 stm32f4_i2c_handle_write(i2c_dev);
630 struct stm32f4_i2c_dev *i2c_dev = data;
631 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
635 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
640 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
650 reg = i2c_dev->base + STM32F4_I2C_CR1;
654 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
661 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
665 stm32f4_i2c_disable_irq(i2c_dev);
666 complete(&i2c_dev->complete);
673 * @i2c_dev: Controller's private data
678 static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev,
682 struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg;
683 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1;
694 reinit_completion(&i2c_dev->complete);
698 stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask);
701 ret = stm32f4_i2c_wait_free_bus(i2c_dev);
709 timeout = wait_for_completion_timeout(&i2c_dev->complete,
710 i2c_dev->adap.timeout);
728 struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
731 ret = clk_enable(i2c_dev->clk);
733 dev_err(i2c_dev->dev, "Failed to enable clock\n");
738 ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0,
741 clk_disable(i2c_dev->clk);
759 struct stm32f4_i2c_dev *i2c_dev;
766 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
767 if (!i2c_dev)
771 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
772 if (IS_ERR(i2c_dev->base))
773 return PTR_ERR(i2c_dev->base);
787 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
788 if (IS_ERR(i2c_dev->clk)) {
790 return PTR_ERR(i2c_dev->clk);
792 ret = clk_prepare_enable(i2c_dev->clk);
794 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
808 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
811 i2c_dev->speed = STM32_I2C_SPEED_FAST;
813 i2c_dev->dev = &pdev->dev;
816 pdev->name, i2c_dev);
824 pdev->name, i2c_dev);
831 ret = stm32f4_i2c_hw_config(i2c_dev);
835 adap = &i2c_dev->adap;
836 i2c_set_adapdata(adap, i2c_dev);
845 init_completion(&i2c_dev->complete);
851 platform_set_drvdata(pdev, i2c_dev);
853 clk_disable(i2c_dev->clk);
855 dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n");
860 clk_disable_unprepare(i2c_dev->clk);
866 struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
868 i2c_del_adapter(&i2c_dev->adap);
870 clk_unprepare(i2c_dev->clk);