Lines Matching refs:i2c
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
86 /* i2c controller state */
127 .name = "s3c2410-i2c",
130 .name = "s3c2440-i2c",
133 .name = "s3c2440-hdmiphy-i2c",
139 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
143 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
144 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
145 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
147 { .compatible = "samsung,exynos5-sata-phy-i2c",
173 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
175 dev_dbg(i2c->dev, "master_complete %d\n", ret);
177 i2c->msg_ptr = 0;
178 i2c->msg = NULL;
179 i2c->msg_idx++;
180 i2c->msg_num = 0;
182 i2c->msg_idx = ret;
184 if (!(i2c->quirks & QUIRK_POLL))
185 wake_up(&i2c->wait);
188 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
192 tmp = readl(i2c->regs + S3C2410_IICCON);
193 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
196 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
200 tmp = readl(i2c->regs + S3C2410_IICCON);
201 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
205 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
209 tmp = readl(i2c->regs + S3C2410_IICCON);
210 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
213 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
217 tmp = readl(i2c->regs + S3C2410_IICCON);
218 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
221 static bool is_ack(struct s3c24xx_i2c *i2c)
226 unsigned long tmp = readl(i2c->regs + S3C2410_IICCON);
237 if (!(readl(i2c->regs + S3C2410_IICSTAT)
243 dev_err(i2c->dev, "ack was not received\n");
250 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
270 s3c24xx_i2c_enable_ack(i2c);
272 iiccon = readl(i2c->regs + S3C2410_IICCON);
273 writel(stat, i2c->regs + S3C2410_IICSTAT);
275 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
276 writeb(addr, i2c->regs + S3C2410_IICDS);
282 ndelay(i2c->tx_setup);
284 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
285 writel(iiccon, i2c->regs + S3C2410_IICCON);
288 writel(stat, i2c->regs + S3C2410_IICSTAT);
291 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
293 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
295 dev_dbg(i2c->dev, "STOP\n");
331 if (i2c->quirks & QUIRK_HDMIPHY) {
338 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
340 i2c->state = STATE_STOP;
342 s3c24xx_i2c_master_complete(i2c, ret);
343 s3c24xx_i2c_disable_irq(i2c);
354 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
356 return i2c->msg_idx >= (i2c->msg_num - 1);
362 static inline int is_msglast(struct s3c24xx_i2c *i2c)
369 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
372 return i2c->msg_ptr == i2c->msg->len-1;
378 static inline int is_msgend(struct s3c24xx_i2c *i2c)
380 return i2c->msg_ptr >= i2c->msg->len;
386 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
392 switch (i2c->state) {
395 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
399 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
400 s3c24xx_i2c_disable_irq(i2c);
406 * bus, or started a new i2c message
409 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
411 dev_dbg(i2c->dev, "ack was not received\n");
412 s3c24xx_i2c_stop(i2c, -ENXIO);
416 if (i2c->msg->flags & I2C_M_RD)
417 i2c->state = STATE_READ;
419 i2c->state = STATE_WRITE;
423 * as this is used by the i2c probe to find devices.
425 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
426 s3c24xx_i2c_stop(i2c, 0);
430 if (i2c->state == STATE_READ)
443 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
445 dev_dbg(i2c->dev, "WRITE: No Ack\n");
447 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
454 if (!is_msgend(i2c)) {
455 byte = i2c->msg->buf[i2c->msg_ptr++];
456 writeb(byte, i2c->regs + S3C2410_IICDS);
465 ndelay(i2c->tx_setup);
467 } else if (!is_lastmsg(i2c)) {
468 /* we need to go to the next i2c message */
470 dev_dbg(i2c->dev, "WRITE: Next Message\n");
472 i2c->msg_ptr = 0;
473 i2c->msg_idx++;
474 i2c->msg++;
477 if (i2c->msg->flags & I2C_M_NOSTART) {
479 if (i2c->msg->flags & I2C_M_RD) {
485 dev_dbg(i2c->dev,
487 s3c24xx_i2c_stop(i2c, -EINVAL);
494 s3c24xx_i2c_message_start(i2c, i2c->msg);
495 i2c->state = STATE_START;
500 s3c24xx_i2c_stop(i2c, 0);
510 byte = readb(i2c->regs + S3C2410_IICDS);
511 i2c->msg->buf[i2c->msg_ptr++] = byte;
514 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
515 i2c->msg->len += byte;
517 if (is_msglast(i2c)) {
520 if (is_lastmsg(i2c))
521 s3c24xx_i2c_disable_ack(i2c);
523 } else if (is_msgend(i2c)) {
528 if (is_lastmsg(i2c)) {
530 dev_dbg(i2c->dev, "READ: Send Stop\n");
532 s3c24xx_i2c_stop(i2c, 0);
535 dev_dbg(i2c->dev, "READ: Next Transfer\n");
537 i2c->msg_ptr = 0;
538 i2c->msg_idx++;
539 i2c->msg++;
549 tmp = readl(i2c->regs + S3C2410_IICCON);
551 writel(tmp, i2c->regs + S3C2410_IICCON);
561 struct s3c24xx_i2c *i2c = dev_id;
565 status = readl(i2c->regs + S3C2410_IICSTAT);
569 dev_err(i2c->dev, "deal with arbitration loss\n");
572 if (i2c->state == STATE_IDLE) {
573 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
575 tmp = readl(i2c->regs + S3C2410_IICCON);
577 writel(tmp, i2c->regs + S3C2410_IICCON);
585 i2c_s3c_irq_nextbyte(i2c, status);
600 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
605 tmp = readl(i2c->regs + S3C2410_IICSTAT);
607 writel(tmp, i2c->regs + S3C2410_IICSTAT);
610 tmp = readl(i2c->regs + S3C2410_IICCON);
613 writel(tmp, i2c->regs + S3C2410_IICCON);
618 * get the i2c bus for a master transaction
620 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
626 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
638 * wait for the i2c bus to become idle.
640 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
649 dev_dbg(i2c->dev, "waiting for bus idle\n");
655 * end of a transaction. However, really slow i2c devices can stretch
662 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
665 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
682 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
686 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
690 * this starts an i2c transfer
692 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
698 ret = s3c24xx_i2c_set_master(i2c);
700 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
705 i2c->msg = msgs;
706 i2c->msg_num = num;
707 i2c->msg_ptr = 0;
708 i2c->msg_idx = 0;
709 i2c->state = STATE_START;
711 s3c24xx_i2c_enable_irq(i2c);
712 s3c24xx_i2c_message_start(i2c, msgs);
714 if (i2c->quirks & QUIRK_POLL) {
715 while ((i2c->msg_num != 0) && is_ack(i2c)) {
716 unsigned long stat = readl(i2c->regs + S3C2410_IICSTAT);
718 i2c_s3c_irq_nextbyte(i2c, stat);
720 stat = readl(i2c->regs + S3C2410_IICSTAT);
722 dev_err(i2c->dev, "deal with arbitration loss\n");
725 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
728 ret = i2c->msg_idx;
735 dev_dbg(i2c->dev, "timeout\n");
737 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
740 if (i2c->quirks & QUIRK_HDMIPHY)
743 s3c24xx_i2c_wait_idle(i2c);
745 s3c24xx_i2c_disable_bus(i2c);
748 i2c->state = STATE_IDLE;
754 * first port of call from the i2c bus code when an message needs
755 * transferring across the i2c bus.
760 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
764 ret = clk_enable(i2c->clk);
770 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
773 clk_disable(i2c->clk);
777 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
782 clk_disable(i2c->clk);
786 /* declare our i2c functionality */
793 /* i2c bus registration info */
832 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
834 struct s3c2410_platform_i2c *pdata = i2c->pdata;
835 unsigned long clkin = clk_get_rate(i2c->clk);
841 i2c->clkrate = clkin;
844 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
853 dev_err(i2c->dev,
861 iiccon = readl(i2c->regs + S3C2410_IICCON);
868 if (i2c->quirks & QUIRK_POLL)
871 writel(iiccon, i2c->regs + S3C2410_IICCON);
873 if (i2c->quirks & QUIRK_S3C2440) {
886 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
887 writel(sda_delay, i2c->regs + S3C2440_IICLC);
900 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
905 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
914 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
915 ret = s3c24xx_i2c_clockrate(i2c, &got);
916 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
919 dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
921 dev_info(i2c->dev, "setting freq %d\n", got);
927 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
929 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
931 return cpufreq_register_notifier(&i2c->freq_transition,
935 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
937 cpufreq_unregister_notifier(&i2c->freq_transition,
942 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
947 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
953 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
957 if (i2c->quirks & QUIRK_NO_GPIO)
961 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
963 if (IS_ERR(i2c->gpios[i])) {
964 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
972 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
981 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
988 pdata = i2c->pdata;
992 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
994 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
996 writel(0, i2c->regs + S3C2410_IICCON);
997 writel(0, i2c->regs + S3C2410_IICSTAT);
1001 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1002 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1006 /* todo - check that the i2c lines aren't being dragged anywhere */
1008 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1009 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1010 readl(i2c->regs + S3C2410_IICCON));
1020 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1022 struct s3c2410_platform_i2c *pdata = i2c->pdata;
1028 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1029 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1030 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1031 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1034 * Exynos5's legacy i2c controller and new high speed i2c
1037 * If nodes for first four channels of legacy i2c controller
1041 id = of_alias_get_id(np, "i2c");
1042 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1044 if (IS_ERR(i2c->sysreg))
1047 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1051 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1056 struct s3c24xx_i2c *i2c;
1069 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1070 if (!i2c)
1073 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1074 if (!i2c->pdata)
1077 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1078 i2c->sysreg = ERR_PTR(-ENOENT);
1080 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1082 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1084 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1085 i2c->adap.owner = THIS_MODULE;
1086 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1087 i2c->adap.retries = 2;
1088 i2c->adap.class = I2C_CLASS_DEPRECATED;
1089 i2c->tx_setup = 50;
1091 init_waitqueue_head(&i2c->wait);
1094 i2c->dev = &pdev->dev;
1095 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1096 if (IS_ERR(i2c->clk)) {
1101 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1105 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1107 if (IS_ERR(i2c->regs))
1108 return PTR_ERR(i2c->regs);
1111 i2c->regs, res);
1113 /* setup info block for the i2c core */
1114 i2c->adap.algo_data = i2c;
1115 i2c->adap.dev.parent = &pdev->dev;
1116 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1118 /* inititalise the i2c gpio lines */
1119 if (i2c->pdata->cfg_gpio)
1120 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1121 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1124 /* initialise the i2c controller */
1125 ret = clk_prepare_enable(i2c->clk);
1131 ret = s3c24xx_i2c_init(i2c);
1132 clk_disable(i2c->clk);
1135 clk_unprepare(i2c->clk);
1143 if (!(i2c->quirks & QUIRK_POLL)) {
1144 i2c->irq = ret = platform_get_irq(pdev, 0);
1147 clk_unprepare(i2c->clk);
1151 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1152 0, dev_name(&pdev->dev), i2c);
1154 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1155 clk_unprepare(i2c->clk);
1160 ret = s3c24xx_i2c_register_cpufreq(i2c);
1163 clk_unprepare(i2c->clk);
1173 i2c->adap.nr = i2c->pdata->bus_num;
1174 i2c->adap.dev.of_node = pdev->dev.of_node;
1176 platform_set_drvdata(pdev, i2c);
1180 ret = i2c_add_numbered_adapter(&i2c->adap);
1183 s3c24xx_i2c_deregister_cpufreq(i2c);
1184 clk_unprepare(i2c->clk);
1188 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1194 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1196 clk_unprepare(i2c->clk);
1200 s3c24xx_i2c_deregister_cpufreq(i2c);
1202 i2c_del_adapter(&i2c->adap);
1210 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1212 i2c_mark_adapter_suspended(&i2c->adap);
1214 if (!IS_ERR(i2c->sysreg))
1215 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1222 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1225 if (!IS_ERR(i2c->sysreg))
1226 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1228 ret = clk_enable(i2c->clk);
1231 s3c24xx_i2c_init(i2c);
1232 clk_disable(i2c->clk);
1233 i2c_mark_adapter_resumed(&i2c->adap);
1255 .name = "s3c-i2c",