Lines Matching refs:master
112 u16 master;
134 struct cci_master master[NUM_MASTERS];
148 complete(&cci->master[0].irq_complete);
149 if (cci->master[1].master)
150 complete(&cci->master[1].irq_complete);
157 cci->master[0].status = 0;
158 complete(&cci->master[0].irq_complete);
165 cci->master[1].status = 0;
166 complete(&cci->master[1].irq_complete);
186 cci->master[0].status = -ENXIO;
188 cci->master[0].status = -EIO;
197 cci->master[1].status = -ENXIO;
199 cci->master[1].status = -EIO;
210 struct cci_master *master;
214 dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num);
219 master = &cci->master[master_num];
221 reinit_completion(&master->irq_complete);
224 if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) {
236 * master[0].xxx for waiting on it.
238 reinit_completion(&cci->master[0].irq_complete);
241 if (!wait_for_completion_timeout(&cci->master[0].irq_complete,
268 int mode = cci->master[i].mode;
271 if (!cci->master[i].cci)
295 static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
299 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
300 writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
302 reinit_completion(&cci->master[master].irq_complete);
303 val = BIT(master * 2 + queue);
306 if (!wait_for_completion_timeout(&cci->master[master].irq_complete,
308 dev_err(cci->dev, "master %d queue %d timeout\n",
309 master, queue);
315 return cci->master[master].status;
318 static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
322 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
330 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
332 return cci_run_queue(cci, master, queue);
335 static int cci_i2c_read(struct cci *cci, u16 master,
347 ret = cci_validate_queue(cci, master, queue);
352 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
355 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
357 ret = cci_run_queue(cci, master, queue);
361 words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
370 val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
388 static int cci_i2c_write(struct cci *cci, u16 master,
400 ret = cci_validate_queue(cci, master, queue);
405 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
417 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
421 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
423 return cci_run_queue(cci, master, queue);
438 ret = cci_i2c_read(cci, cci_master->master,
442 ret = cci_i2c_write(cci, cci_master->master,
558 cci->master[idx].adap.quirks = &cci->data->quirks;
559 cci->master[idx].adap.algo = &cci_algo;
560 cci->master[idx].adap.dev.parent = dev;
561 cci->master[idx].adap.dev.of_node = of_node_get(child);
562 cci->master[idx].master = idx;
563 cci->master[idx].cci = cci;
565 i2c_set_adapdata(&cci->master[idx].adap, &cci->master[idx]);
566 snprintf(cci->master[idx].adap.name,
567 sizeof(cci->master[idx].adap.name), "Qualcomm-CCI");
569 cci->master[idx].mode = I2C_MODE_STANDARD;
573 cci->master[idx].mode = I2C_MODE_FAST;
575 cci->master[idx].mode = I2C_MODE_FAST_PLUS;
578 init_completion(&cci->master[idx].irq_complete);
647 if (!cci->master[i].cci)
650 ret = i2c_add_adapter(&cci->master[i].adap);
652 of_node_put(cci->master[i].adap.dev.of_node);
664 if (cci->master[i].cci) {
665 i2c_del_adapter(&cci->master[i].adap);
666 of_node_put(cci->master[i].adap.dev.of_node);
683 if (cci->master[i].cci) {
684 i2c_del_adapter(&cci->master[i].adap);
685 of_node_put(cci->master[i].adap.dev.of_node);