Lines Matching refs:bus
30 * of the bus.
319 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
322 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
328 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
331 static void npcm_i2c_init_params(struct npcm_i2c *bus)
333 bus->stop_ind = I2C_NO_STATUS_IND;
334 bus->rd_size = 0;
335 bus->wr_size = 0;
336 bus->rd_ind = 0;
337 bus->wr_ind = 0;
338 bus->read_block_use = false;
339 bus->int_time_stamp = 0;
340 bus->PEC_use = false;
341 bus->PEC_mask = 0;
343 if (bus->slave)
344 bus->master_or_slave = I2C_SLAVE;
348 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
350 iowrite8(data, bus->reg + NPCM_I2CSDA);
353 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
355 return ioread8(bus->reg + NPCM_I2CSDA);
360 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
362 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
367 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
369 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
372 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
374 if (bus->operation == I2C_READ_OPER)
375 return bus->rd_ind;
376 if (bus->operation == I2C_WRITE_OPER)
377 return bus->wr_ind;
382 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
384 return bus->wr_size == 0 && bus->rd_size == 0;
387 static void npcm_i2c_disable(struct npcm_i2c *bus)
396 iowrite8(0, bus->reg + npcm_i2caddr[i]);
400 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
402 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
404 bus->state = I2C_DISABLE;
407 static void npcm_i2c_enable(struct npcm_i2c *bus)
409 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
412 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
413 bus->state = I2C_IDLE;
417 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
422 val = ioread8(bus->reg + NPCM_I2CCST3);
424 iowrite8(val, bus->reg + NPCM_I2CCST3);
426 val = ioread8(bus->reg + NPCM_I2CCTL1);
432 iowrite8(val, bus->reg + NPCM_I2CCTL1);
435 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
439 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
448 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
452 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
461 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
465 val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
467 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
470 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
474 val = ioread8(bus->reg + NPCM_I2CTXF_STS);
476 iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
479 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
483 val = ioread8(bus->reg + NPCM_I2CRXF_STS);
485 iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
488 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
492 val = ioread8(bus->reg + NPCM_I2CCTL1);
498 iowrite8(val, bus->reg + NPCM_I2CCTL1);
501 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
505 val = ioread8(bus->reg + NPCM_I2CCTL1);
508 iowrite8(val, bus->reg + NPCM_I2CCTL1);
511 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
521 val = ioread8(bus->reg + NPCM_I2CCTL1);
524 iowrite8(val, bus->reg + NPCM_I2CCTL1);
526 if (!bus->fifo_use)
529 npcm_i2c_select_bank(bus, I2C_BANK_1);
531 if (bus->operation == I2C_READ_OPER)
532 npcm_i2c_clear_rx_fifo(bus);
534 npcm_i2c_clear_tx_fifo(bus);
535 npcm_i2c_clear_fifo_int(bus);
536 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
539 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
543 val = ioread8(bus->reg + NPCM_I2CCTL1);
549 iowrite8(val, bus->reg + NPCM_I2CCTL1);
552 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
556 val = ioread8(bus->reg + NPCM_I2CCTL1);
559 iowrite8(val, bus->reg + NPCM_I2CCTL1);
562 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
568 iowrite8(val, bus->reg + NPCM_I2CST);
572 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
577 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
583 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
586 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
595 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
600 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
603 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
608 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
612 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
618 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
619 npcm_i2c_slave_int_enable(bus, enable);
625 static void npcm_i2c_reset(struct npcm_i2c *bus)
636 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
638 npcm_i2c_disable(bus);
639 npcm_i2c_enable(bus);
643 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
646 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
647 iowrite8(0xFF, bus->reg + NPCM_I2CST);
650 npcm_i2c_eob_int(bus, false);
653 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
656 if (bus->slave) {
657 addr = bus->slave->addr;
658 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
663 npcm_i2c_clear_master_status(bus);
665 bus->state = I2C_IDLE;
668 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
670 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
673 static void npcm_i2c_callback(struct npcm_i2c *bus,
680 msgs = bus->msgs;
681 msgs_num = bus->msgs_num;
689 if (completion_done(&bus->cmd_complete))
694 bus->cmd_err = bus->msgs_num;
698 if (bus->msgs) {
709 bus->cmd_err = -ENXIO;
714 bus->cmd_err = -EAGAIN;
724 bus->operation = I2C_NO_OPER;
726 if (bus->slave)
727 bus->master_or_slave = I2C_SLAVE;
730 complete(&bus->cmd_complete);
733 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
735 if (bus->operation == I2C_WRITE_OPER)
737 ioread8(bus->reg + NPCM_I2CTXF_STS));
738 if (bus->operation == I2C_READ_OPER)
740 ioread8(bus->reg + NPCM_I2CRXF_STS));
744 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
752 size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
754 if (bus->wr_ind < bus->wr_size)
755 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
757 npcm_i2c_wr_byte(bus, 0xFF);
758 size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
767 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
771 if (!bus->fifo_use)
773 npcm_i2c_select_bank(bus, I2C_BANK_1);
774 npcm_i2c_clear_tx_fifo(bus);
775 npcm_i2c_clear_rx_fifo(bus);
790 if (bus->rd_ind == 0 && bus->read_block_use) {
796 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
803 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL);
805 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
807 npcm_i2c_clear_tx_fifo(bus);
811 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
816 data = npcm_i2c_rd_byte(bus);
817 if (bus->rd_ind < bus->rd_size)
818 bus->rd_buf[bus->rd_ind++] = data;
822 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
825 if (!npcm_i2c_is_master(bus))
828 npcm_i2c_eob_int(bus, true);
829 npcm_i2c_master_stop(bus);
830 npcm_i2c_clear_master_status(bus);
834 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
839 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
841 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
846 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
854 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
855 iowrite8(0, bus->reg + npcm_i2caddr[i]);
861 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
867 npcm_i2c_clear_fifo_int(bus);
868 npcm_i2c_clear_tx_fifo(bus);
869 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
870 while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) {
871 if (bus->slv_wr_size <= 0)
873 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
874 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
875 bus->slv_wr_ind++;
876 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
877 bus->slv_wr_size--;
881 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
885 if (!bus->slave)
889 data = npcm_i2c_rd_byte(bus);
891 bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE;
892 bus->slv_rd_buf[bus->slv_rd_ind] = data;
893 bus->slv_rd_ind++;
896 if (bus->slv_rd_ind == 1 && bus->read_block_use)
897 bus->slv_rd_size = data + bus->PEC_use + 1;
901 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
906 int ret = bus->slv_wr_ind;
910 if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
912 if (bus->state == I2C_SLAVE_MATCH) {
913 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
914 bus->state = I2C_OPER_STARTED;
916 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
918 ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE;
919 bus->slv_wr_buf[ind] = value;
920 bus->slv_wr_size++;
925 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
929 for (i = 0; i < bus->slv_rd_ind; i++)
930 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
931 &bus->slv_rd_buf[i]);
936 if (bus->slv_rd_ind) {
937 bus->slv_wr_size = 0;
938 bus->slv_wr_ind = 0;
941 bus->slv_rd_ind = 0;
942 bus->slv_rd_size = bus->adap.quirks->max_read_len;
944 npcm_i2c_clear_fifo_int(bus);
945 npcm_i2c_clear_rx_fifo(bus);
948 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
951 bus->state = I2C_OPER_STARTED;
952 bus->operation = I2C_READ_OPER;
953 bus->slv_rd_size = nread;
954 bus->slv_rd_ind = 0;
956 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
957 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
958 npcm_i2c_clear_tx_fifo(bus);
959 npcm_i2c_clear_rx_fifo(bus);
962 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
968 bus->operation = I2C_WRITE_OPER;
971 npcm_i2c_slave_get_wr_buf(bus);
972 npcm_i2c_write_fifo_slave(bus, nwrite);
980 * to the FIFO and onward to the bus.
981 * NACK on read will be once reached to bus->adap->quirks->max_read_len.
986 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
991 ioread8(bus->reg + NPCM_I2CTXF_STS));
995 bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
999 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1000 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1002 if (bus->slv_wr_ind < 0)
1003 bus->slv_wr_ind += I2C_HW_FIFO_SIZE;
1006 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1008 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1013 bus->operation = I2C_WRITE_OPER;
1014 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1015 bus->slv_wr_buf);
1023 bus->operation = I2C_READ_OPER;
1024 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1025 bus->stop_ind = I2C_SLAVE_RCV_IND;
1026 npcm_i2c_slave_send_rd_buf(bus);
1027 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1028 bus->slv_rd_buf);
1032 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1036 u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1040 bus->stop_ind = I2C_NACK_IND;
1041 npcm_i2c_slave_wr_buf_sync(bus);
1042 if (bus->fifo_use)
1045 bus->reg + NPCM_I2CFIF_CTS);
1048 bus->stop_ind = I2C_NO_STATUS_IND;
1049 bus->operation = I2C_NO_OPER;
1050 bus->own_slave_addr = 0xFF;
1056 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1064 * Check whether bus arbitration or Start or Stop during data
1065 * xfer bus arbitration problem should not result in recovery
1067 bus->stop_ind = I2C_BUS_ERR_IND;
1069 /* wait for bus busy before clear fifo */
1070 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1072 bus->state = I2C_IDLE;
1078 if (completion_done(&bus->cmd_complete) == false) {
1079 bus->cmd_err = -EIO;
1080 complete(&bus->cmd_complete);
1082 bus->own_slave_addr = 0xFF;
1083 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1089 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1091 bus->stop_ind = I2C_SLAVE_DONE_IND;
1093 if (bus->operation == I2C_READ_OPER)
1094 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1097 npcm_i2c_slave_send_rd_buf(bus);
1100 bus->stop_ind = I2C_NO_STATUS_IND;
1107 bus->operation = I2C_NO_OPER;
1108 bus->own_slave_addr = 0xFF;
1109 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1110 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1111 if (bus->fifo_use) {
1112 npcm_i2c_clear_fifo_int(bus);
1113 npcm_i2c_clear_rx_fifo(bus);
1114 npcm_i2c_clear_tx_fifo(bus);
1117 bus->reg + NPCM_I2CFIF_CTS);
1119 bus->state = I2C_IDLE;
1124 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1125 ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1126 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1127 bus->master_or_slave = I2C_SLAVE;
1128 if (bus->operation == I2C_READ_OPER)
1129 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1130 bus->operation = I2C_WRITE_OPER;
1131 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1134 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1135 npcm_i2c_slave_rd_wr(bus);
1144 bus->master_or_slave = I2C_SLAVE;
1145 npcm_i2c_clear_fifo_int(bus);
1146 npcm_i2c_clear_rx_fifo(bus);
1147 npcm_i2c_clear_tx_fifo(bus);
1148 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1149 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
1151 bus->operation = I2C_WRITE_OPER;
1153 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1155 bus->operation = I2C_READ_OPER;
1157 if (bus->own_slave_addr == 0xFF) {
1159 val = ioread8(bus->reg + NPCM_I2CCST);
1166 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1167 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1178 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1180 bus->own_slave_addr = addr;
1181 if (bus->PEC_mask & BIT(info))
1182 bus->PEC_use = true;
1184 bus->PEC_use = false;
1187 bus->own_slave_addr = 0;
1189 bus->own_slave_addr = 0x61;
1200 if ((bus->state == I2C_OPER_STARTED &&
1201 bus->operation == I2C_READ_OPER &&
1202 bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1203 bus->stop_ind == I2C_SLAVE_RCV_IND) {
1205 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1210 bus->stop_ind = I2C_SLAVE_XMIT_IND;
1212 bus->stop_ind = I2C_SLAVE_RCV_IND;
1213 bus->state = I2C_SLAVE_MATCH;
1214 npcm_i2c_slave_rd_wr(bus);
1215 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1221 (bus->fifo_use &&
1222 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1223 npcm_i2c_slave_rd_wr(bus);
1224 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1233 npcm_i2c_eob_int(bus, false);
1234 npcm_i2c_clear_master_status(bus);
1243 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1245 bus->slave = client;
1247 if (!bus->slave)
1253 spin_lock_irqsave(&bus->lock, lock_flags);
1255 npcm_i2c_init_params(bus);
1256 bus->slv_rd_size = 0;
1257 bus->slv_wr_size = 0;
1258 bus->slv_rd_ind = 0;
1259 bus->slv_wr_ind = 0;
1261 bus->PEC_use = true;
1263 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1264 client->addr, bus->PEC_use);
1266 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1267 npcm_i2c_clear_fifo_int(bus);
1268 npcm_i2c_clear_rx_fifo(bus);
1269 npcm_i2c_clear_tx_fifo(bus);
1270 npcm_i2c_slave_int_enable(bus, true);
1272 spin_unlock_irqrestore(&bus->lock, lock_flags);
1278 struct npcm_i2c *bus = client->adapter->algo_data;
1281 spin_lock_irqsave(&bus->lock, lock_flags);
1282 if (!bus->slave) {
1283 spin_unlock_irqrestore(&bus->lock, lock_flags);
1286 npcm_i2c_slave_int_enable(bus, false);
1287 npcm_i2c_remove_slave_addr(bus, client->addr);
1288 bus->slave = NULL;
1289 spin_unlock_irqrestore(&bus->lock, lock_flags);
1294 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1300 fifo_bytes = npcm_i2c_fifo_usage(bus);
1301 rcount = bus->rd_size - bus->rd_ind;
1315 bus->state = I2C_STOP_PENDING;
1316 bus->stop_ind = ind;
1317 npcm_i2c_eob_int(bus, true);
1319 npcm_i2c_master_stop(bus);
1320 npcm_i2c_read_fifo(bus, fifo_bytes);
1322 npcm_i2c_read_fifo(bus, fifo_bytes);
1323 rcount = bus->rd_size - bus->rd_ind;
1324 npcm_i2c_set_fifo(bus, rcount, -1);
1328 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1332 if (bus->fifo_use)
1333 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1336 if (bus->wr_ind == bus->wr_size) {
1337 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1347 if (bus->rd_size == 0) {
1349 npcm_i2c_eob_int(bus, true);
1350 bus->state = I2C_STOP_PENDING;
1351 bus->stop_ind = I2C_MASTER_DONE_IND;
1352 npcm_i2c_master_stop(bus);
1354 npcm_i2c_wr_byte(bus, 0xFF);
1358 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1360 npcm_i2c_master_start(bus);
1368 if (bus->rd_size == 1)
1369 npcm_i2c_stall_after_start(bus, true);
1372 bus->operation = I2C_READ_OPER;
1374 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1378 if (!bus->fifo_use || bus->wr_size == 1) {
1379 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1381 wcount = bus->wr_size - bus->wr_ind;
1382 npcm_i2c_set_fifo(bus, -1, wcount);
1384 npcm_i2c_write_to_fifo_master(bus, wcount);
1389 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1395 block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1401 if (bus->rd_ind == 0) { /* first byte handling: */
1402 if (bus->read_block_use) {
1404 data = npcm_i2c_rd_byte(bus);
1406 bus->rd_size = data + block_extra_bytes_size;
1407 bus->rd_buf[bus->rd_ind++] = data;
1410 if (bus->fifo_use) {
1411 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1413 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1416 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1417 npcm_i2c_stall_after_start(bus, false);
1419 npcm_i2c_clear_tx_fifo(bus);
1420 npcm_i2c_master_fifo_read(bus);
1423 if (bus->rd_size == block_extra_bytes_size &&
1424 bus->read_block_use) {
1425 bus->state = I2C_STOP_PENDING;
1426 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1427 bus->cmd_err = -EIO;
1428 npcm_i2c_eob_int(bus, true);
1429 npcm_i2c_master_stop(bus);
1430 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1432 npcm_i2c_master_fifo_read(bus);
1437 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1439 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1440 npcm_i2c_nack(bus);
1441 bus->stop_ind = I2C_BUS_ERR_IND;
1442 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1446 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1450 if (bus->nack_cnt < ULLONG_MAX)
1451 bus->nack_cnt++;
1453 if (bus->fifo_use) {
1458 if (bus->operation == I2C_WRITE_OPER)
1459 bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1462 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1466 bus->stop_ind = I2C_NACK_IND;
1468 if (npcm_i2c_is_master(bus)) {
1470 npcm_i2c_eob_int(bus, false);
1471 npcm_i2c_master_stop(bus);
1474 npcm_i2c_rd_byte(bus);
1477 * The bus is released from stall only after the SW clears
1480 npcm_i2c_clear_master_status(bus);
1481 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1483 /* verify no status bits are still set after bus is released */
1484 npcm_i2c_clear_master_status(bus);
1486 bus->state = I2C_IDLE;
1490 * In such case, the bus is released from stall only after the
1493 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1497 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1499 if (bus->ber_cnt < ULLONG_MAX)
1500 bus->ber_cnt++;
1501 bus->stop_ind = I2C_BUS_ERR_IND;
1502 if (npcm_i2c_is_master(bus)) {
1503 npcm_i2c_master_abort(bus);
1505 npcm_i2c_clear_master_status(bus);
1508 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1510 bus->cmd_err = -EAGAIN;
1511 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1513 bus->state = I2C_IDLE;
1517 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1519 npcm_i2c_eob_int(bus, false);
1520 bus->state = I2C_IDLE;
1521 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1525 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1527 if (npcm_i2c_is_quick(bus)) {
1528 bus->state = I2C_STOP_PENDING;
1529 bus->stop_ind = I2C_MASTER_DONE_IND;
1530 npcm_i2c_eob_int(bus, true);
1531 npcm_i2c_master_stop(bus);
1532 } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1537 npcm_i2c_nack(bus);
1541 npcm_i2c_stall_after_start(bus, false);
1544 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1548 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1552 if (!npcm_i2c_is_master(bus))
1555 if (bus->state == I2C_IDLE) {
1556 bus->stop_ind = I2C_WAKE_UP_IND;
1558 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1563 npcm_i2c_stall_after_start(bus, true);
1565 npcm_i2c_stall_after_start(bus, false);
1573 if (bus->wr_size == 0 && bus->rd_size == 1)
1574 npcm_i2c_stall_after_start(bus, true);
1579 npcm_i2c_select_bank(bus, I2C_BANK_1);
1581 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1586 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1590 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1599 if (bus->wr_size)
1600 npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1602 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1604 bus->state = I2C_OPER_STARTED;
1606 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1607 npcm_i2c_wr_byte(bus, bus->dest_addr);
1609 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1613 bus->operation = I2C_WRITE_OPER;
1614 npcm_i2c_irq_master_handler_write(bus);
1616 bus->operation = I2C_READ_OPER;
1617 npcm_i2c_irq_master_handler_read(bus);
1622 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1627 i2cst = ioread8(bus->reg + NPCM_I2CST);
1630 npcm_i2c_irq_handle_nmatch(bus);
1635 npcm_i2c_irq_handle_nack(bus);
1641 npcm_i2c_irq_handle_ber(bus);
1647 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1649 ioread8(bus->reg + NPCM_I2CCST3)))) {
1650 npcm_i2c_irq_handle_eob(bus);
1656 npcm_i2c_irq_handle_stall_after_start(bus);
1662 (bus->fifo_use &&
1663 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1664 npcm_i2c_irq_handle_sda(bus, i2cst);
1678 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1683 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1684 bus->num, bus->dest_addr);
1685 npcm_i2c_reset(bus);
1689 npcm_i2c_int_enable(bus, false);
1690 npcm_i2c_disable(bus);
1691 npcm_i2c_enable(bus);
1692 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1693 npcm_i2c_clear_tx_fifo(bus);
1694 npcm_i2c_clear_rx_fifo(bus);
1695 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1696 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1697 npcm_i2c_stall_after_start(bus, false);
1700 npcm_i2c_select_bank(bus, I2C_BANK_1);
1703 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1706 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1707 npcm_i2c_set_fifo(bus, -1, 0);
1712 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1724 npcm_i2c_wr_byte(bus, bus->dest_addr);
1725 npcm_i2c_master_start(bus);
1730 if (npcm_i2c_is_master(bus) > 0) {
1732 npcm_i2c_master_stop(bus);
1736 npcm_i2c_reset(bus);
1737 npcm_i2c_int_enable(bus, true);
1744 if (bus->rec_fail_cnt < ULLONG_MAX)
1745 bus->rec_fail_cnt++;
1747 if (bus->rec_succ_cnt < ULLONG_MAX)
1748 bus->rec_succ_cnt++;
1756 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1757 struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1780 * and bus frequency.
1781 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are simetric.
1782 * 400kHz bus requires assymetric HT and LT. A different equation is recomended
1786 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1797 src_clk_khz = bus->apb_clk / 1000;
1799 bus->bus_freq = bus_freq_hz;
1880 bus->reg + NPCM_I2CCTL2);
1884 bus->reg + NPCM_I2CCTL3);
1887 npcm_i2c_select_bank(bus, I2C_BANK_0);
1895 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1896 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1898 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1901 iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1904 npcm_i2c_select_bank(bus, I2C_BANK_1);
1909 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1916 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1920 npcm_i2c_int_enable(bus, false);
1921 npcm_i2c_disable(bus);
1924 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1925 bus->fifo_use = true;
1926 npcm_i2c_select_bank(bus, I2C_BANK_0);
1927 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1929 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1930 npcm_i2c_select_bank(bus, I2C_BANK_1);
1932 bus->fifo_use = false;
1936 ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1938 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1943 npcm_i2c_enable(bus);
1944 bus->state = I2C_IDLE;
1945 val = ioread8(bus->reg + NPCM_I2CCTL1);
1947 iowrite8(val, bus->reg + NPCM_I2CCTL1);
1949 npcm_i2c_reset(bus);
1952 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1953 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1954 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1955 npcm_i2c_get_SCL(&bus->adap));
1959 npcm_i2c_int_enable(bus, true);
1963 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1969 bus->state = I2C_DISABLE;
1970 bus->master_or_slave = I2C_SLAVE;
1971 bus->int_time_stamp = 0;
1973 bus->slave = NULL;
1983 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
1994 struct npcm_i2c *bus = dev_id;
1996 if (npcm_i2c_is_master(bus))
1997 bus->master_or_slave = I2C_MASTER;
1999 if (bus->master_or_slave == I2C_MASTER) {
2000 bus->int_time_stamp = jiffies;
2001 if (!npcm_i2c_int_master_handler(bus))
2005 if (bus->slave) {
2006 bus->master_or_slave = I2C_SLAVE;
2007 if (npcm_i2c_int_slave_handler(bus))
2012 npcm_i2c_clear_master_status(bus);
2017 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2022 if (bus->state != I2C_IDLE) {
2023 bus->cmd_err = -EBUSY;
2026 bus->dest_addr = slave_addr << 1;
2027 bus->wr_buf = write_data;
2028 bus->wr_size = nwrite;
2029 bus->wr_ind = 0;
2030 bus->rd_buf = read_data;
2031 bus->rd_size = nread;
2032 bus->rd_ind = 0;
2033 bus->PEC_use = 0;
2037 bus->PEC_use = use_PEC;
2039 bus->read_block_use = use_read_block;
2041 bus->operation = I2C_READ_OPER;
2043 bus->operation = I2C_WRITE_OPER;
2044 if (bus->fifo_use) {
2047 npcm_i2c_select_bank(bus, I2C_BANK_1);
2049 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2052 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2055 bus->state = I2C_IDLE;
2056 npcm_i2c_stall_after_start(bus, true);
2057 npcm_i2c_master_start(bus);
2064 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2076 if (bus->state == I2C_DISABLE) {
2077 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2120 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2121 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2123 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2130 * we must clear slave address immediately when the bus is not
2134 spin_lock_irqsave(&bus->lock, flags);
2135 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2137 if (!bus_busy && bus->slave)
2138 iowrite8((bus->slave->addr & 0x7F),
2139 bus->reg + NPCM_I2CADDR1);
2141 spin_unlock_irqrestore(&bus->lock, flags);
2146 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2147 npcm_i2c_reset(bus);
2152 npcm_i2c_init_params(bus);
2153 bus->dest_addr = slave_addr;
2154 bus->msgs = msgs;
2155 bus->msgs_num = num;
2156 bus->cmd_err = 0;
2157 bus->read_block_use = read_block;
2159 reinit_completion(&bus->cmd_complete);
2161 npcm_i2c_int_enable(bus, true);
2163 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2166 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2170 if (bus->timeout_cnt < ULLONG_MAX)
2171 bus->timeout_cnt++;
2172 if (bus->master_or_slave == I2C_MASTER) {
2174 bus->cmd_err = -EIO;
2175 bus->state = I2C_IDLE;
2180 /* if there was BER, check if need to recover the bus: */
2181 if (bus->cmd_err == -EAGAIN)
2182 bus->cmd_err = i2c_recover_bus(adap);
2189 else if (bus->cmd_err &&
2190 (NPCM_I2CRXF_CTL_LAST_PEC & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2191 npcm_i2c_reset(bus);
2194 npcm_i2c_stall_after_start(bus, false);
2195 npcm_i2c_eob_int(bus, false);
2199 if (bus->slave)
2200 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2201 bus->reg + NPCM_I2CADDR1);
2203 npcm_i2c_int_enable(bus, false);
2205 return bus->cmd_err;
2236 struct npcm_i2c *bus)
2245 debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2246 debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2247 debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2248 debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2249 debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2251 bus->debugfs = d;
2256 struct npcm_i2c *bus;
2264 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2265 if (!bus)
2268 bus->dev = &pdev->dev;
2270 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2275 bus->apb_clk = clk_get_rate(i2c_clk);
2286 bus->reg = devm_platform_ioremap_resource(pdev, 0);
2287 if (IS_ERR(bus->reg))
2288 return PTR_ERR(bus->reg);
2290 spin_lock_init(&bus->lock);
2291 init_completion(&bus->cmd_complete);
2293 adap = &bus->adap;
2299 adap->algo_data = bus;
2308 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2309 dev_name(bus->dev), bus);
2313 ret = __npcm_i2c_init(bus, pdev);
2319 i2c_set_adapdata(adap, bus);
2321 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2322 bus->num);
2323 ret = i2c_add_numbered_adapter(&bus->adap);
2327 platform_set_drvdata(pdev, bus);
2328 npcm_i2c_init_debugfs(pdev, bus);
2335 struct npcm_i2c *bus = platform_get_drvdata(pdev);
2337 debugfs_remove_recursive(bus->debugfs);
2338 spin_lock_irqsave(&bus->lock, lock_flags);
2339 npcm_i2c_disable(bus);
2340 spin_unlock_irqrestore(&bus->lock, lock_flags);
2341 i2c_del_adapter(&bus->adap);