Lines Matching defs:drv_data
173 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
178 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
185 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
186 drv_data->addr2 = (u32)msg->addr & 0xff;
188 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
189 drv_data->addr2 = 0;
203 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
205 if (drv_data->offload_enabled) {
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
208 writel(0, drv_data->reg_base +
210 writel(0, drv_data->reg_base +
214 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
215 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
216 drv_data->reg_base + drv_data->reg_offsets.clock);
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
218 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
220 drv_data->reg_base + drv_data->reg_offsets.control);
221 drv_data->state = MV64XXX_I2C_STATE_IDLE;
225 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
232 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
233 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
242 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
243 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
248 if (drv_data->msg->flags & I2C_M_TEN) {
249 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
250 drv_data->state =
257 if ((drv_data->bytes_left == 0)
258 || (drv_data->aborting
259 && (drv_data->byte_posn != 0))) {
260 if (drv_data->send_stop || drv_data->aborting) {
261 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
262 drv_data->state = MV64XXX_I2C_STATE_IDLE;
264 drv_data->action =
266 drv_data->state =
270 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
271 drv_data->state =
273 drv_data->bytes_left--;
279 if (drv_data->msg->flags & I2C_M_TEN) {
280 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
281 drv_data->state =
287 if (drv_data->bytes_left == 0) {
288 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
289 drv_data->state = MV64XXX_I2C_STATE_IDLE;
295 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
297 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
298 drv_data->bytes_left--;
300 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
302 if ((drv_data->bytes_left == 1) || drv_data->aborting)
303 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
307 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
308 drv_data->state = MV64XXX_I2C_STATE_IDLE;
315 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
316 drv_data->state = MV64XXX_I2C_STATE_IDLE;
317 drv_data->rc = -ENXIO;
321 dev_err(&drv_data->adapter.dev,
324 drv_data->state, status, drv_data->msg->addr,
325 drv_data->msg->flags);
326 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
327 mv64xxx_i2c_hw_init(drv_data);
328 drv_data->rc = -EIO;
332 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
334 drv_data->msg = drv_data->msgs;
335 drv_data->byte_posn = 0;
336 drv_data->bytes_left = drv_data->msg->len;
337 drv_data->aborting = 0;
338 drv_data->rc = 0;
340 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
341 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
342 drv_data->reg_base + drv_data->reg_offsets.control);
346 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
348 switch(drv_data->action) {
351 BUG_ON(drv_data->num_msgs == 0);
353 drv_data->msgs++;
354 drv_data->num_msgs--;
355 mv64xxx_i2c_send_start(drv_data);
357 if (drv_data->errata_delay)
365 drv_data->send_stop = drv_data->num_msgs == 1;
369 writel(drv_data->cntl_bits,
370 drv_data->reg_base + drv_data->reg_offsets.control);
374 writel(drv_data->addr1,
375 drv_data->reg_base + drv_data->reg_offsets.data);
376 writel(drv_data->cntl_bits,
377 drv_data->reg_base + drv_data->reg_offsets.control);
381 writel(drv_data->addr2,
382 drv_data->reg_base + drv_data->reg_offsets.data);
383 writel(drv_data->cntl_bits,
384 drv_data->reg_base + drv_data->reg_offsets.control);
388 writel(drv_data->msg->buf[drv_data->byte_posn++],
389 drv_data->reg_base + drv_data->reg_offsets.data);
390 writel(drv_data->cntl_bits,
391 drv_data->reg_base + drv_data->reg_offsets.control);
395 drv_data->msg->buf[drv_data->byte_posn++] =
396 readl(drv_data->reg_base + drv_data->reg_offsets.data);
397 writel(drv_data->cntl_bits,
398 drv_data->reg_base + drv_data->reg_offsets.control);
402 drv_data->msg->buf[drv_data->byte_posn++] =
403 readl(drv_data->reg_base + drv_data->reg_offsets.data);
404 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
405 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
406 drv_data->reg_base + drv_data->reg_offsets.control);
407 drv_data->block = 0;
408 if (drv_data->errata_delay)
411 wake_up(&drv_data->waitq);
416 dev_err(&drv_data->adapter.dev,
418 drv_data->action);
419 drv_data->rc = -EIO;
422 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
423 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
424 drv_data->reg_base + drv_data->reg_offsets.control);
425 drv_data->block = 0;
426 wake_up(&drv_data->waitq);
432 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
437 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
438 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
444 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
448 cause = readl(drv_data->reg_base +
453 status = readl(drv_data->reg_base +
457 drv_data->rc = -EIO;
461 drv_data->rc = 0;
467 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
468 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
469 drv_data->msgs++;
470 drv_data->num_msgs--;
476 else if (drv_data->num_msgs == 2 &&
477 !(drv_data->msgs[0].flags & I2C_M_RD) &&
478 drv_data->msgs[1].flags & I2C_M_RD) {
479 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
480 drv_data->msgs += 2;
481 drv_data->num_msgs -= 2;
485 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
486 writel(0, drv_data->reg_base +
488 drv_data->block = 0;
490 wake_up(&drv_data->waitq);
498 struct mv64xxx_i2c_data *drv_data = dev_id;
502 spin_lock(&drv_data->lock);
504 if (drv_data->offload_enabled)
505 rc = mv64xxx_i2c_intr_offload(drv_data);
507 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
509 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
510 mv64xxx_i2c_fsm(drv_data, status);
511 mv64xxx_i2c_do_action(drv_data);
513 if (drv_data->irq_clear_inverted)
514 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
515 drv_data->reg_base + drv_data->reg_offsets.control);
519 spin_unlock(&drv_data->lock);
532 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
538 time_left = wait_event_timeout(drv_data->waitq,
539 !drv_data->block, drv_data->adapter.timeout);
541 spin_lock_irqsave(&drv_data->lock, flags);
543 drv_data->rc = -ETIMEDOUT;
546 drv_data->rc = time_left; /* errno value */
550 if (abort && drv_data->block) {
551 drv_data->aborting = 1;
552 spin_unlock_irqrestore(&drv_data->lock, flags);
554 time_left = wait_event_timeout(drv_data->waitq,
555 !drv_data->block, drv_data->adapter.timeout);
557 if ((time_left <= 0) && drv_data->block) {
558 drv_data->state = MV64XXX_I2C_STATE_IDLE;
559 dev_err(&drv_data->adapter.dev,
561 "time_left: %d\n", drv_data->block,
563 mv64xxx_i2c_hw_init(drv_data);
566 spin_unlock_irqrestore(&drv_data->lock, flags);
570 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
575 spin_lock_irqsave(&drv_data->lock, flags);
577 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
579 drv_data->send_stop = is_last;
580 drv_data->block = 1;
581 mv64xxx_i2c_send_start(drv_data);
582 spin_unlock_irqrestore(&drv_data->lock, flags);
584 mv64xxx_i2c_wait_for_completion(drv_data);
585 return drv_data->rc;
589 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
591 struct i2c_msg *msg = drv_data->msgs;
596 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
597 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
601 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
603 struct i2c_msg *msgs = drv_data->msgs;
604 int num = drv_data->num_msgs;
608 spin_lock_irqsave(&drv_data->lock, flags);
623 mv64xxx_i2c_prepare_tx(drv_data);
646 mv64xxx_i2c_prepare_tx(drv_data);
650 drv_data->block = 1;
651 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
652 spin_unlock_irqrestore(&drv_data->lock, flags);
654 mv64xxx_i2c_wait_for_completion(drv_data);
656 return drv_data->rc;
666 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
668 struct i2c_msg *msgs = drv_data->msgs;
669 int num = drv_data->num_msgs;
671 if (!drv_data->offload_enabled)
713 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
716 BUG_ON(drv_data->msgs != NULL);
717 drv_data->msgs = msgs;
718 drv_data->num_msgs = num;
720 if (mv64xxx_i2c_can_offload(drv_data))
721 rc = mv64xxx_i2c_offload_xfer(drv_data);
723 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
728 drv_data->num_msgs = 0;
729 drv_data->msgs = NULL;
758 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
761 if (drv_data->clk_n_base_0)
768 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
776 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
779 drv_data->freq_m = m;
780 drv_data->freq_n = n;
792 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
804 if (IS_ERR(drv_data->clk)) {
808 tclk = clk_get_rate(drv_data->clk);
815 drv_data->clk_n_base_0 = true;
817 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
822 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
823 if (IS_ERR(drv_data->rstc)) {
824 rc = PTR_ERR(drv_data->rstc);
827 reset_control_deassert(drv_data->rstc);
832 drv_data->adapter.timeout = HZ;
838 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
845 drv_data->offload_enabled = true;
848 drv_data->errata_delay = true;
852 drv_data->offload_enabled = false;
855 drv_data->errata_delay = true;
859 drv_data->irq_clear_inverted = true;
866 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
876 struct mv64xxx_i2c_data *drv_data;
883 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
885 if (!drv_data)
888 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
889 if (IS_ERR(drv_data->reg_base))
890 return PTR_ERR(drv_data->reg_base);
892 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
893 sizeof(drv_data->adapter.name));
895 init_waitqueue_head(&drv_data->waitq);
896 spin_lock_init(&drv_data->lock);
899 drv_data->clk = devm_clk_get(&pd->dev, NULL);
900 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
902 if (!IS_ERR(drv_data->clk))
903 clk_prepare_enable(drv_data->clk);
905 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
906 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
908 if (!IS_ERR(drv_data->reg_clk))
909 clk_prepare_enable(drv_data->reg_clk);
911 drv_data->irq = platform_get_irq(pd, 0);
914 drv_data->freq_m = pdata->freq_m;
915 drv_data->freq_n = pdata->freq_n;
916 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
917 drv_data->offload_enabled = false;
918 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
920 rc = mv64xxx_of_config(drv_data, &pd->dev);
924 if (drv_data->irq < 0) {
925 rc = drv_data->irq;
929 drv_data->adapter.dev.parent = &pd->dev;
930 drv_data->adapter.algo = &mv64xxx_i2c_algo;
931 drv_data->adapter.owner = THIS_MODULE;
932 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
933 drv_data->adapter.nr = pd->id;
934 drv_data->adapter.dev.of_node = pd->dev.of_node;
935 platform_set_drvdata(pd, drv_data);
936 i2c_set_adapdata(&drv_data->adapter, drv_data);
938 mv64xxx_i2c_hw_init(drv_data);
940 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
941 MV64XXX_I2C_CTLR_NAME, drv_data);
943 dev_err(&drv_data->adapter.dev,
945 drv_data->irq, rc);
947 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
948 dev_err(&drv_data->adapter.dev,
956 free_irq(drv_data->irq, drv_data);
958 reset_control_assert(drv_data->rstc);
960 clk_disable_unprepare(drv_data->reg_clk);
961 clk_disable_unprepare(drv_data->clk);
969 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
971 i2c_del_adapter(&drv_data->adapter);
972 free_irq(drv_data->irq, drv_data);
973 reset_control_assert(drv_data->rstc);
974 clk_disable_unprepare(drv_data->reg_clk);
975 clk_disable_unprepare(drv_data->clk);
983 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
985 mv64xxx_i2c_hw_init(drv_data);