Lines Matching refs:sample_cnt
591 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
603 unsigned int sample_cnt)
608 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
655 (sample_cnt << 12) | (high_cnt << 8);
657 i2c->ac_timing.ltiming |= (sample_cnt << 12) |
672 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
673 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
693 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
698 * sample_cnt and step_cn
706 unsigned int sample_cnt;
724 /* Search for the best pair (sample_cnt, step_cnt) with
725 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
727 * sample_cnt * step_cnt >= opt_div
728 * optimizing for sample_cnt * step_cnt being minimal
730 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
731 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
732 cnt_mul = step_cnt * sample_cnt;
738 target_speed, step_cnt - 1, sample_cnt - 1);
743 base_sample_cnt = sample_cnt;
753 sample_cnt = base_sample_cnt;
756 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
765 *timing_sample_cnt = sample_cnt - 1;
774 unsigned int sample_cnt;
807 &sample_cnt);
812 (sample_cnt << 12) | (step_cnt << 8);
817 (sample_cnt << 12) | (step_cnt << 9);