Lines Matching defs:pdmabase
239 void __iomem *pdmabase; /* dma base address*/
491 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
493 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
496 i2c->pdmabase + OFFSET_RST);
500 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
503 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
505 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
912 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
913 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
929 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
932 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
933 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
935 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
936 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
952 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
955 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
956 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
958 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
959 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
998 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1001 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1004 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1005 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1006 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1007 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1010 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1214 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
1215 if (IS_ERR(i2c->pdmabase))
1216 return PTR_ERR(i2c->pdmabase);