Lines Matching refs:MPC_I2C_SR
43 #define MPC_I2C_SR 0x0c
95 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
97 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
98 writeb(0, i2c->base + MPC_I2C_SR);
117 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
141 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
150 cmd_err = readb(i2c->base + MPC_I2C_SR);
151 writeb(0, i2c->base + MPC_I2C_SR);
191 void __iomem *addr = i2c->base + MPC_I2C_SR;
229 val = readb(i2c->base + MPC_I2C_SR);
535 writeb(0, i2c->base + MPC_I2C_SR);
655 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
662 u8 status = readb(i2c->base + MPC_I2C_SR);
667 i2c->base + MPC_I2C_SR);
696 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
698 u8 status = readb(i2c->base + MPC_I2C_SR);
703 i2c->base + MPC_I2C_SR);