Lines Matching defs:i2c_clk
256 int i2c_clk = i2c->speed;
262 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
266 cnt_period = dev_clk_khz / i2c_clk;
268 if (i2c_clk <= 100)
282 if (i2c_clk <= 100) {
311 * 1i2c_clk = 10^6 / dev_clk_khz
312 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
313 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
315 * The actual hold time is (SDAHD + 1) * (i2c_clk period).
320 if (i2c_clk <= 100) { /* standard mode */