Lines Matching refs:data
176 static void at91_twi_write_data_dma_callback(void *data)
178 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
240 * DMA controller is triggered when at least 4 data can be
276 * If we are in this case, it means there is garbage data in RHR, so
317 static void at91_twi_read_data_dma_callback(void *data)
319 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
359 * DMA controller is triggered when at least 4 data can be
401 * weird. There is some magic about RXRDY flag! When a data has been
404 * the stop command not on the last data but on the second last one.
407 * transfer is done and we have read the last data. It might happen
408 * when the i2c slave device sends too quickly data after receiving the
409 * ack from the master. The data has been almost received before having
412 * the RXRDY interrupt first in order to not keep garbage data in the
439 * the DMA controller to write the next data into the THR. Then the
445 * next data into the THR, hence starting a new transfer: the I2C slave
460 * is triggered by the TXRDY bit to write the next data into the THR,
461 * this data actually won't go on the I2C bus hence a second NACK is not
496 * controller from sending new data on the i2c bus after a NACK
498 * triggering the DMA controller for new data but it is more than
501 * these new data won't be sent to the i2c bus but they will remain
565 * command too late and then to receive extra data.
764 * trigger the XDMAC when at least 4 data can be written into the TX
768 * read data from the RX FIFO.
902 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);