Lines Matching refs:clk_high
819 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
841 * SCL_high = clk_high + 1
845 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
846 * The documentation recommends clk_high >= clk_high_max / 2 and
856 clk_high = clk_high_low_mask;
864 clk_high = tmp - clk_low;
866 if (clk_high)
867 clk_high--;
874 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
885 * clk_high and clk_low are each 3 bits wide, so each can hold a max
894 * clk_high and clk_low are each 4 bits wide, so each can hold a max