Lines Matching defs:clk_low
819 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
842 * SCL_low = clk_low + 1
845 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
847 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
855 clk_low = clk_high_low_mask;
863 clk_low = tmp / 2;
864 clk_high = tmp - clk_low;
869 if (clk_low)
870 clk_low--;
876 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
885 * clk_high and clk_low are each 3 bits wide, so each can hold a max
894 * clk_high and clk_low are each 4 bits wide, so each can hold a max