Lines Matching refs:gth

20 #include "gth.h"
26  * @gth:	backlink to the GTH device
33 	struct gth_device	*gth;
61 static void gth_output_set(struct gth_device *gth, int port,
68 	val = ioread32(gth->base + reg);
71 	iowrite32(val, gth->base + reg);
74 static unsigned int gth_output_get(struct gth_device *gth, int port)
80 	val = ioread32(gth->base + reg);
87 static void gth_smcfreq_set(struct gth_device *gth, int port,
94 	val = ioread32(gth->base + reg);
97 	iowrite32(val, gth->base + reg);
100 static unsigned int gth_smcfreq_get(struct gth_device *gth, int port)
106 	val = ioread32(gth->base + reg);
119 	struct gth_device	*gth;
124 gth_master_set(struct gth_device *gth, unsigned int master, int port)
135 	val = ioread32(gth->base + reg);
139 	iowrite32(val, gth->base + reg);
148 	struct gth_device *gth = ma->gth;
152 	spin_lock(&gth->gth_lock);
153 	port = gth->master[ma->master];
154 	spin_unlock(&gth->gth_lock);
170 	struct gth_device *gth = ma->gth;
179 	spin_lock(&gth->gth_lock);
182 	old_port = gth->master[ma->master];
184 		gth->master[ma->master] = -1;
185 		clear_bit(ma->master, gth->output[old_port].master);
191 		if (gth->output[old_port].output->active)
192 			gth_master_set(gth, ma->master, -1);
198 		if (!gth->output[port].output) {
203 		set_bit(ma->master, gth->output[port].master);
206 		if (gth->output[port].output->active)
207 			gth_master_set(gth, ma->master, port);
210 	gth->master[ma->master] = port;
213 	spin_unlock(&gth->gth_lock);
220 	struct gth_device	*gth;
235 	unsigned int	(*get)(struct gth_device *gth, int port);
236 	void		(*set)(struct gth_device *gth, int port,
251 gth_output_parm_set(struct gth_device *gth, int port, unsigned int parm,
254 	unsigned int config = output_parms[parm].get(gth, port);
260 	output_parms[parm].set(gth, port, config);
264 gth_output_parm_get(struct gth_device *gth, int port, unsigned int parm)
266 	unsigned int config = output_parms[parm].get(gth, port);
278 static int intel_th_gth_reset(struct gth_device *gth)
283 	reg = ioread32(gth->base + REG_GTH_SCRPD0);
289 	iowrite32(reg, gth->base + REG_GTH_SCRPD0);
293 		if (gth_output_parm_get(gth, port, TH_OUTPUT_PARM(port)) ==
297 		gth_output_set(gth, port, 0);
298 		gth_smcfreq_set(gth, port, 16);
301 	iowrite32(0, gth->base + REG_GTH_DESTOVR);
305 		iowrite32(0, gth->base + REG_GTH_SWDEST0 + i * 4);
308 	iowrite32(0, gth->base + REG_GTH_SCR);
309 	iowrite32(0xfc, gth->base + REG_GTH_SCR2);
312 	iowrite32(CTS_EVENT_ENABLE_IF_ANYTHING, gth->base + REG_CTS_C0S0_EN);
314 		  CTS_ACTION_CONTROL_TRIGGER, gth->base + REG_CTS_C0S0_ACT);
329 	struct gth_device *gth = oa->gth;
334 	spin_lock(&gth->gth_lock);
336 			 gth_output_parm_get(gth, oa->port, oa->parm));
337 	spin_unlock(&gth->gth_lock);
350 	struct gth_device *gth = oa->gth;
358 	spin_lock(&gth->gth_lock);
359 	gth_output_parm_set(gth, oa->port, oa->parm, config);
360 	spin_unlock(&gth->gth_lock);
367 static int intel_th_master_attributes(struct gth_device *gth)
373 	attrs = devm_kcalloc(gth->dev, nattrs, sizeof(void *), GFP_KERNEL);
377 	master_attrs = devm_kcalloc(gth->dev, nattrs,
386 		name = devm_kasprintf(gth->dev, GFP_KERNEL, "%d%s", i,
399 		master_attrs[i].gth = gth;
403 	gth->master_group.name	= "masters";
404 	gth->master_group.attrs = attrs;
406 	return sysfs_create_group(&gth->dev->kobj, &gth->master_group);
409 static int intel_th_output_attributes(struct gth_device *gth)
417 	attrs = devm_kcalloc(gth->dev, nattrs, sizeof(void *), GFP_KERNEL);
421 	out_attrs = devm_kcalloc(gth->dev, nattrs,
432 			name = devm_kasprintf(gth->dev, GFP_KERNEL, "%d_%s", i,
452 			out_attrs[idx].gth = gth;
458 	gth->output_group.name	= "outputs";
459 	gth->output_group.attrs = attrs;
461 	return sysfs_create_group(&gth->dev->kobj, &gth->output_group);
466  * @gth:		GTH device
473 static void intel_th_gth_stop(struct gth_device *gth,
485 	iowrite32(0, gth->base + REG_GTH_SCR);
486 	iowrite32(scr2, gth->base + REG_GTH_SCR2);
491 		reg = ioread32(gth->base + REG_GTH_STAT);
496 		dev_dbg(gth->dev, "timeout waiting for GTH[%d] PLE\n",
504 	iowrite32(0xfc, gth->base + REG_GTH_SCR2);
509  * @gth:	GTH device
514 static void intel_th_gth_start(struct gth_device *gth,
522 	iowrite32(scr, gth->base + REG_GTH_SCR);
523 	iowrite32(0, gth->base + REG_GTH_SCR2);
538 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
542 	spin_lock(&gth->gth_lock);
545 	for_each_set_bit(master, gth->output[output->port].master,
547 		gth_master_set(gth, master, -1);
549 	spin_unlock(&gth->gth_lock);
551 	intel_th_gth_stop(gth, output, true);
553 	reg = ioread32(gth->base + REG_GTH_SCRPD0);
555 	iowrite32(reg, gth->base + REG_GTH_SCRPD0);
558 static void gth_tscu_resync(struct gth_device *gth)
562 	reg = ioread32(gth->base + REG_TSCU_TSUCTRL);
564 	iowrite32(reg, gth->base + REG_TSCU_TSUCTRL);
570 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
578 	     count && !(gth_output_get(gth, output->port) & BIT(5)); count--)
593 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
598 	spin_lock(&gth->gth_lock);
599 	for_each_set_bit(master, gth->output[output->port].master,
601 		gth_master_set(gth, master, output->port);
605 	spin_unlock(&gth->gth_lock);
608 		gth_tscu_resync(gth);
610 	scrpd = ioread32(gth->base + REG_GTH_SCRPD0);
612 	iowrite32(scrpd, gth->base + REG_GTH_SCRPD0);
614 	intel_th_gth_start(gth, output);
628 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
633 	iowrite32(0, gth->base + REG_CTS_CTL);
634 	iowrite32(CTS_CTL_SEQUENCER_ENABLE, gth->base + REG_CTS_CTL);
638 		reg = ioread32(gth->base + REG_CTS_STAT);
645 	iowrite32(0, gth->base + REG_CTS_CTL);
647 	intel_th_gth_stop(gth, output, false);
648 	intel_th_gth_start(gth, output);
665 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
675 		if (gth->output[i].port_type != othdev->output.type)
687 	spin_lock(&gth->gth_lock);
690 	gth->output[i].output = &othdev->output;
691 	spin_unlock(&gth->gth_lock);
704 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
711 	spin_lock(&gth->gth_lock);
714 	gth->output[port].output = NULL;
716 		if (gth->master[master] == port)
717 			gth->master[master] = -1;
718 	spin_unlock(&gth->gth_lock);
724 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
734 	spin_lock(&gth->gth_lock);
735 	if (gth->master[master] == -1) {
736 		set_bit(master, gth->output[port].master);
737 		gth->master[master] = port;
739 	spin_unlock(&gth->gth_lock);
748 	struct gth_device *gth;
761 	gth = devm_kzalloc(dev, sizeof(*gth), GFP_KERNEL);
762 	if (!gth)
765 	gth->dev = dev;
766 	gth->base = base;
767 	spin_lock_init(&gth->gth_lock);
769 	dev_set_drvdata(dev, gth);
780 	ret = intel_th_gth_reset(gth);
791 		gth->master[i] = -1;
794 		gth->output[i].gth = gth;
795 		gth->output[i].index = i;
796 		gth->output[i].port_type =
797 			gth_output_parm_get(gth, i, TH_OUTPUT_PARM(port));
798 		if (gth->output[i].port_type == GTH_NONE)
801 		ret = intel_th_output_enable(th, gth->output[i].port_type);
807 	if (intel_th_output_attributes(gth) ||
808 	    intel_th_master_attributes(gth)) {
811 		if (gth->output_group.attrs)
812 			sysfs_remove_group(&gth->dev->kobj, &gth->output_group);
821 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
823 	sysfs_remove_group(&gth->dev->kobj, &gth->output_group);
824 	sysfs_remove_group(&gth->dev->kobj, &gth->master_group);
838 		.name	= "gth",