Lines Matching defs:tmp
716 u16 tmp = data->temp[nr];
717 return sprintf(buf, "%ld\n", (nr) ? (long) LM75_TEMP_FROM_REG(tmp)
718 : (long) TEMP_FROM_REG(tmp));
727 u16 tmp = data->temp_max[nr];
728 return sprintf(buf, "%ld\n", (nr) ? (long) LM75_TEMP_FROM_REG(tmp)
729 : (long) TEMP_FROM_REG(tmp));
739 u16 tmp = data->temp_max_hyst[nr];
740 return sprintf(buf, "%ld\n", (nr) ? (long) LM75_TEMP_FROM_REG(tmp)
741 : (long) TEMP_FROM_REG(tmp));
750 u16 tmp;
758 tmp = (nr) ? LM75_TEMP_TO_REG(val) : TEMP_TO_REG(val);
760 data->temp_max[nr] = tmp;
761 w83627hf_write_value(data, w83627hf_reg_temp_over[nr], tmp);
772 u16 tmp;
780 tmp = (nr) ? LM75_TEMP_TO_REG(val) : TEMP_TO_REG(val);
782 data->temp_max_hyst[nr] = tmp;
783 w83627hf_write_value(data, w83627hf_reg_temp_hyst[nr], tmp);
1185 u32 tmp;
1196 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1198 tmp | BIT_SCFG1[nr]);
1199 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
1201 tmp | BIT_SCFG2[nr]);
1205 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1207 tmp | BIT_SCFG1[nr]);
1208 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
1210 tmp & ~BIT_SCFG2[nr]);
1218 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1220 tmp & ~BIT_SCFG1[nr]);
1726 u8 tmp;
1753 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1755 if (!(tmp & BIT_SCFG1[i - 1])) {
1771 tmp = w83627hf_read_value(data, W83627HF_REG_TEMP2_CONFIG);
1772 if (tmp & 0x01) {
1776 tmp & 0xfe);
1781 tmp = w83627hf_read_value(data,
1783 if (tmp & 0x01) {
1787 W83627HF_REG_TEMP3_CONFIG, tmp & 0xfe);
1799 tmp = w83627hf_read_value(data, W83781D_REG_VBAT);
1800 if (!(tmp & 0x01))
1801 w83627hf_write_value(data, W83781D_REG_VBAT, tmp | 0x01);
1855 u8 tmp = w83627hf_read_value(data,
1859 tmp &= 0xf0;
1860 data->pwm[i] = tmp;
1866 u8 tmp = w83627hf_read_value(data,
1868 data->pwm_freq[0] = tmp & 0x07;
1869 data->pwm_freq[1] = (tmp >> 4) & 0x07;
1881 u8 tmp = w83627hf_read_value(data,
1884 ((tmp >> W83627THF_PWM_ENABLE_SHIFT[i])