Lines Matching defs:w83627ehf_write_value
423 static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
460 return w83627ehf_write_value(data, reg, value);
474 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
477 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
484 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
487 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
492 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
495 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
500 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
503 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
509 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
620 w83627ehf_write_value(data,
709 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
783 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
812 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
832 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
845 w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
866 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
904 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
933 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
985 w83627ehf_write_value(data, REG[nr], val); \
1024 w83627ehf_write_value(data, REG[nr], val); \
1102 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1103 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1228 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
1240 w83627ehf_write_value(data,
1248 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
2001 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
2003 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
2011 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
2028 w83627ehf_write_value(data,
2034 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);