Lines Matching refs:data
183 struct npcm7xx_pwm_fan_data *data;
210 static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,
220 mutex_lock(&data->pwm_lock[module]);
223 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));
224 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));
244 mutex_unlock(&data->pwm_lock[module]);
258 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));
259 mutex_unlock(&data->pwm_lock[module]);
264 static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,
275 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {
277 spin_lock_irqsave(&data->fan_lock[fan], flags);
279 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
280 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
292 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
295 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
299 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
305 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
309 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,
314 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
317 spin_unlock_irqrestore(&data->fan_lock[fan], flags);
327 struct npcm7xx_pwm_fan_data *data;
330 data = from_timer(data, t, fan_timer);
336 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;
340 NPCM7XX_FAN_REG_TICLR(data->fan_base, i));
342 if (data->fan_present[i * 2]) {
344 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));
345 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);
347 if (data->fan_present[(i * 2) + 1]) {
349 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));
350 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);
354 data->fan_select++;
355 data->fan_select &= 0x3;
358 data->fan_timer.expires = jiffies +
360 add_timer(&data->fan_timer);
363 static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,
372 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));
374 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));
377 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
379 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {
381 data->fan_dev[fan_id].fan_st_flg =
385 data->fan_dev[fan_id].fan_cnt_tmp = 0;
386 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {
391 data->fan_dev[fan_id].fan_cnt_tmp +=
394 data->fan_dev[fan_id].fan_st_flg++;
397 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {
398 data->fan_dev[fan_id].fan_cnt_tmp +=
402 data->fan_dev[fan_id].fan_cnt =
403 data->fan_dev[fan_id].fan_cnt_tmp /
406 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;
409 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
413 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
414 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
418 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
422 static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,
451 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
455 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));
459 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));
461 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
465 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
472 data->fan_dev[fan_id].fan_cnt = 0;
476 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,
483 struct npcm7xx_pwm_fan_data *data = dev_id;
488 module = irq - data->fan_irq[0];
489 spin_lock_irqsave(&data->fan_lock[module], flags);
491 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));
493 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);
494 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);
495 spin_unlock_irqrestore(&data->fan_lock[module], flags);
499 spin_unlock_irqrestore(&data->fan_lock[module], flags);
507 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
514 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));
524 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
531 err = npcm7xx_pwm_config_set(data, channel, (u16)val);
543 const struct npcm7xx_pwm_fan_data *data = _data;
545 if (!data->pwm_present[channel])
559 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);
564 if (data->fan_dev[channel].fan_cnt <= 0)
565 return data->fan_dev[channel].fan_cnt;
568 if (data->fan_dev[channel].fan_cnt > 0 &&
569 data->fan_dev[channel].fan_pls_per_rev > 0)
570 *val = ((data->input_clk_freq * 60) /
571 (data->fan_dev[channel].fan_cnt *
572 data->fan_dev[channel].fan_pls_per_rev));
581 const struct npcm7xx_pwm_fan_data *data = _data;
583 if (!data->fan_present[channel])
618 static umode_t npcm7xx_is_visible(const void *data,
624 return npcm7xx_pwm_is_visible(data, attr, channel);
626 return npcm7xx_fan_is_visible(data, attr, channel);
673 static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)
678 data->pwm_clk_freq = clk_get_rate(data->pwm_clk);
681 output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT;
697 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));
699 NPCM7XX_PWM_REG_CSR(data->pwm_base, m));
701 NPCM7XX_PWM_REG_CR(data->pwm_base, m));
705 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));
712 static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)
722 NPCM7XX_FAN_REG_TCKC(data->fan_base, md));
725 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));
729 NPCM7XX_FAN_REG_TICLR(data->fan_base, md));
733 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));
738 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));
742 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));
744 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));
748 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));
752 NPCM7XX_FAN_REG_TCPA(data->fan_base, md));
754 NPCM7XX_FAN_REG_TCPB(data->fan_base, md));
758 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));
760 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));
764 data->fan_dev[ch].fan_st_flg = FAN_DISABLE;
765 data->fan_dev[ch].fan_pls_per_rev =
767 data->fan_dev[ch].fan_cnt = 0;
771 apb_clk_freq = clk_get_rate(data->fan_clk);
774 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);
810 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
824 struct npcm7xx_pwm_fan_data *data,
854 cdev->data = data;
857 data->cdev[pwm_port] = cdev;
864 struct npcm7xx_pwm_fan_data *data)
875 data->pwm_present[pwm_port] = true;
876 ret = npcm7xx_pwm_config_set(data, pwm_port,
881 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,
901 data->fan_present[index] = true;
902 data->fan_dev[index].fan_st_flg = FAN_INIT;
912 struct npcm7xx_pwm_fan_data *data;
922 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
923 if (!data)
932 data->pwm_base = devm_ioremap_resource(dev, res);
934 if (IS_ERR(data->pwm_base))
935 return PTR_ERR(data->pwm_base);
937 data->pwm_clk = devm_clk_get(dev, "pwm");
938 if (IS_ERR(data->pwm_clk)) {
940 return PTR_ERR(data->pwm_clk);
949 data->fan_base = devm_ioremap_resource(dev, res);
951 if (IS_ERR(data->fan_base))
952 return PTR_ERR(data->fan_base);
954 data->fan_clk = devm_clk_get(dev, "fan");
955 if (IS_ERR(data->fan_clk)) {
957 return PTR_ERR(data->fan_clk);
960 output_freq = npcm7xx_pwm_init(data);
961 npcm7xx_fan_init(data);
964 mutex_init(&data->pwm_lock[cnt]);
967 spin_lock_init(&data->fan_lock[i]);
969 data->fan_irq[i] = platform_get_irq(pdev, i);
970 if (data->fan_irq[i] < 0)
971 return data->fan_irq[i];
974 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,
975 0, name, (void *)data);
983 ret = npcm7xx_en_pwm_fan(dev, child, data);
992 data, &npcm7xx_chip_info,
1000 if (data->fan_present[i]) {
1002 data->fan_timer.expires = jiffies +
1004 timer_setup(&data->fan_timer,
1006 add_timer(&data->fan_timer);
1012 output_freq, data->input_clk_freq);