Lines Matching refs:BANK_0
35 #define BANK_0 0x00
229 ret = nct7904_read_reg16(data, BANK_0,
253 ret = nct7904_read_reg(data, BANK_0,
309 ret = nct7904_read_reg16(data, BANK_0,
345 ret = nct7904_read_reg(data, BANK_0,
398 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
400 ret = nct7904_read_reg16(data, BANK_0,
403 ret = nct7904_read_reg16(data, BANK_0,
413 ret = nct7904_read_reg(data, BANK_0,
419 ret = nct7904_read_reg(data, BANK_0,
426 ret = nct7904_read_reg(data, BANK_0,
433 ret = nct7904_read_reg(data, BANK_0,
931 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
938 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
956 return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG,
972 ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
977 ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
982 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
990 ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
1031 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
1044 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
1047 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1053 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
1067 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1074 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
1112 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
1117 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
1133 ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);