Lines Matching defs:INA3221_MASK_ENABLE
36 #define INA3221_MASK_ENABLE 0x0f
80 [F_CVRF] = REG_FIELD(INA3221_MASK_ENABLE, 0, 0),
81 [F_WF3] = REG_FIELD(INA3221_MASK_ENABLE, 3, 3),
82 [F_WF2] = REG_FIELD(INA3221_MASK_ENABLE, 4, 4),
83 [F_WF1] = REG_FIELD(INA3221_MASK_ENABLE, 5, 5),
84 [F_SF] = REG_FIELD(INA3221_MASK_ENABLE, 6, 6),
85 [F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7),
86 [F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8),
87 [F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9),
745 regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE),
987 ret = regmap_update_bits(ina->regmap, INA3221_MASK_ENABLE,