Lines Matching defs:sig
203 struct ipu_di_signal_cfg *sig)
205 u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
206 sig->mode.hback_porch + sig->mode.hfront_porch;
207 u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
208 sig->mode.vback_porch + sig->mode.vfront_porch;
220 .cnt_down = sig->mode.hsync_len * 2,
227 .cnt_down = sig->mode.vsync_len * 2,
240 .offset_count = (sig->mode.vsync_len +
241 sig->mode.vback_porch) / 2,
243 .repeat_count = sig->mode.vactive / 2,
248 .offset_count = sig->mode.hsync_len +
249 sig->mode.hback_porch,
251 .repeat_count = sig->mode.hactive,
266 struct ipu_di_signal_cfg *sig, int div)
268 u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
269 sig->mode.hback_porch + sig->mode.hfront_porch;
270 u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
271 sig->mode.vback_porch + sig->mode.vfront_porch;
281 .offset_count = div * sig->v_to_h_sync,
285 .cnt_down = sig->mode.hsync_len * 2,
292 .cnt_down = sig->mode.vsync_len * 2,
296 .offset_count = sig->mode.vsync_len +
297 sig->mode.vback_porch,
299 .repeat_count = sig->mode.vactive,
304 .offset_count = sig->mode.hsync_len +
305 sig->mode.hback_porch,
307 .repeat_count = sig->mode.hactive,
332 .offset_count = sig->mode.vsync_len +
333 sig->mode.vback_porch,
335 .repeat_count = sig->mode.vactive,
341 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
345 .cnt_down = sig->mode.hsync_len * 2,
349 .offset_count = sig->mode.hsync_len +
350 sig->mode.hback_porch,
352 .repeat_count = sig->mode.hactive,
362 .cnt_down = sig->mode.vsync_len * 2,
367 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
371 .cnt_down = sig->mode.hsync_len * 2,
380 .cnt_down = sig->mode.vsync_len * 2,
387 if (sig->hsync_pin == 2 && sig->vsync_pin == 3)
394 const struct ipu_di_signal_cfg *sig)
400 if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
408 if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
428 clk_set_rate(clk, sig->mode.pixelclock);
431 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
448 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
452 error = rate / (sig->mode.pixelclock / 1000);
469 clk_set_rate(clk, sig->mode.pixelclock);
472 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
499 sig->mode.pixelclock,
558 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
565 di->id, sig->mode.hactive, sig->mode.vactive);
570 sig->mode.pixelclock);
574 ipu_di_config_clock(di, sig);
589 if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) {
590 ipu_di_sync_config_interlaced(di, sig);
597 ipu_di_sync_config_noninterlaced(di, sig, div);
605 if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
609 if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
610 di_gen |= ipu_di_gen_polarity(sig->hsync_pin);
611 if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
612 di_gen |= ipu_di_gen_polarity(sig->vsync_pin);
614 if (sig->clk_pol)
625 if (sig->enable_pol)
627 if (sig->data_pol)