Lines Matching refs:ipu
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
29 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
31 return readl(ipu->cm_reg + offset);
34 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
36 writel(value, ipu->cm_reg + offset);
39 int ipu_get_num(struct ipu_soc *ipu)
41 return ipu->id;
45 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
49 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
200 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
204 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
209 mutex_lock(&ipu->channel_lock);
211 list_for_each_entry(channel, &ipu->channels, list) {
225 channel->ipu = ipu;
226 list_add(&channel->list, &ipu->channels);
229 mutex_unlock(&ipu->channel_lock);
237 struct ipu_soc *ipu = channel->ipu;
239 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
241 mutex_lock(&ipu->channel_lock);
246 mutex_unlock(&ipu->channel_lock);
265 struct ipu_soc *ipu = channel->ipu;
268 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
274 struct ipu_soc *ipu = channel->ipu;
278 spin_lock_irqsave(&ipu->lock, flags);
280 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
285 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
289 spin_unlock_irqrestore(&ipu->lock, flags);
319 struct ipu_soc *ipu = channel->ipu;
347 if (bursts && ipu->ipu_type != IPUV3H)
357 spin_lock_irqsave(&ipu->lock, flags);
359 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
362 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
364 spin_unlock_irqrestore(&ipu->lock, flags);
370 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
375 spin_lock_irqsave(&ipu->lock, lock_flags);
377 val = ipu_cm_read(ipu, IPU_DISP_GEN);
384 ipu_cm_write(ipu, val, IPU_DISP_GEN);
386 val = ipu_cm_read(ipu, IPU_CONF);
388 ipu_cm_write(ipu, val, IPU_CONF);
390 spin_unlock_irqrestore(&ipu->lock, lock_flags);
396 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
401 spin_lock_irqsave(&ipu->lock, lock_flags);
403 val = ipu_cm_read(ipu, IPU_CONF);
405 ipu_cm_write(ipu, val, IPU_CONF);
407 val = ipu_cm_read(ipu, IPU_DISP_GEN);
414 ipu_cm_write(ipu, val, IPU_DISP_GEN);
416 spin_unlock_irqrestore(&ipu->lock, lock_flags);
424 struct ipu_soc *ipu = channel->ipu;
427 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
433 struct ipu_soc *ipu = channel->ipu;
437 spin_lock_irqsave(&ipu->lock, flags);
440 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
443 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
446 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
449 spin_unlock_irqrestore(&ipu->lock, flags);
457 struct ipu_soc *ipu = channel->ipu;
461 spin_lock_irqsave(&ipu->lock, flags);
465 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
467 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
469 spin_unlock_irqrestore(&ipu->lock, flags);
475 struct ipu_soc *ipu = channel->ipu;
479 spin_lock_irqsave(&ipu->lock, flags);
481 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
484 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
487 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
490 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
495 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
497 spin_unlock_irqrestore(&ipu->lock, flags);
503 struct ipu_soc *ipu = channel->ipu;
507 spin_lock_irqsave(&ipu->lock, flags);
509 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
511 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
513 spin_unlock_irqrestore(&ipu->lock, flags);
519 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
521 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
527 struct ipu_soc *ipu = channel->ipu;
531 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
544 struct ipu_soc *ipu = channel->ipu;
548 spin_lock_irqsave(&ipu->lock, flags);
551 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
553 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
558 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
560 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
562 ipu_cm_write(ipu, idma_mask(channel->num),
566 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
568 ipu_cm_write(ipu, idma_mask(channel->num),
572 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
575 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
577 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
579 spin_unlock_irqrestore(&ipu->lock, flags);
593 struct ipu_soc *ipu = channel->ipu;
597 spin_lock_irqsave(&ipu->lock, flags);
599 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
604 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
606 spin_unlock_irqrestore(&ipu->lock, flags);
610 static int ipu_memory_reset(struct ipu_soc *ipu)
614 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
617 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
630 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
638 spin_lock_irqsave(&ipu->lock, flags);
640 val = ipu_cm_read(ipu, IPU_CONF);
645 ipu_cm_write(ipu, val, IPU_CONF);
647 spin_unlock_irqrestore(&ipu->lock, flags);
654 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
659 spin_lock_irqsave(&ipu->lock, flags);
661 val = ipu_cm_read(ipu, IPU_CONF);
672 ipu_cm_write(ipu, val, IPU_CONF);
674 spin_unlock_irqrestore(&ipu->lock, flags);
732 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
742 spin_lock_irqsave(&ipu->lock, flags);
745 src_reg = ipu_cm_read(ipu, link->src.reg);
748 ipu_cm_write(ipu, src_reg, link->src.reg);
752 sink_reg = ipu_cm_read(ipu, link->sink.reg);
755 ipu_cm_write(ipu, sink_reg, link->sink.reg);
758 spin_unlock_irqrestore(&ipu->lock, flags);
766 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
776 spin_lock_irqsave(&ipu->lock, flags);
779 src_reg = ipu_cm_read(ipu, link->src.reg);
781 ipu_cm_write(ipu, src_reg, link->src.reg);
785 sink_reg = ipu_cm_read(ipu, link->sink.reg);
787 ipu_cm_write(ipu, sink_reg, link->sink.reg);
790 spin_unlock_irqrestore(&ipu->lock, flags);
798 return ipu_fsu_link(src->ipu, src->num, sink->num);
805 return ipu_fsu_unlink(src->ipu, src->num, sink->num);
874 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
875 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
876 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
877 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
882 static int ipu_submodules_init(struct ipu_soc *ipu,
889 const struct ipu_devtype *devtype = ipu->devtype;
891 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
897 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
904 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
911 ret = ipu_ic_init(ipu, dev,
919 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
927 ret = ipu_image_convert_init(ipu, dev);
933 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
940 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
947 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
954 ret = ipu_dmfc_init(ipu, dev, ipu_base +
961 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
967 ret = ipu_smfc_init(ipu, dev, ipu_base +
977 ipu_dp_exit(ipu);
979 ipu_dmfc_exit(ipu);
981 ipu_dc_exit(ipu);
983 ipu_di_exit(ipu, 1);
985 ipu_di_exit(ipu, 0);
987 ipu_image_convert_exit(ipu);
989 ipu_vdi_exit(ipu);
991 ipu_ic_exit(ipu);
993 ipu_csi_exit(ipu, 1);
995 ipu_csi_exit(ipu, 0);
997 ipu_cpmem_exit(ipu);
1003 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1010 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1011 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1014 irq = irq_linear_revmap(ipu->domain,
1024 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1030 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1037 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1043 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1048 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1052 virq = irq_linear_revmap(ipu->domain, irq);
1054 virq = irq_create_mapping(ipu->domain, irq);
1060 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1063 return ipu_map_irq(ipu, irq_type + channel->num);
1067 static void ipu_submodules_exit(struct ipu_soc *ipu)
1069 ipu_smfc_exit(ipu);
1070 ipu_dp_exit(ipu);
1071 ipu_dmfc_exit(ipu);
1072 ipu_dc_exit(ipu);
1073 ipu_di_exit(ipu, 1);
1074 ipu_di_exit(ipu, 0);
1075 ipu_image_convert_exit(ipu);
1076 ipu_vdi_exit(ipu);
1077 ipu_ic_exit(ipu);
1078 ipu_csi_exit(ipu, 1);
1079 ipu_csi_exit(ipu, 0);
1080 ipu_cpmem_exit(ipu);
1142 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1144 struct device *dev = ipu->dev;
1197 static int ipu_irq_init(struct ipu_soc *ipu)
1213 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1214 &irq_generic_chip_ops, ipu);
1215 if (!ipu->domain) {
1216 dev_err(ipu->dev, "failed to add irq domain\n");
1220 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1223 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1224 irq_domain_remove(ipu->domain);
1230 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1231 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1235 gc = irq_get_domain_generic_chip(ipu->domain, i);
1236 gc->reg_base = ipu->cm_reg;
1246 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1247 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1248 ipu);
1253 static void ipu_irq_exit(struct ipu_soc *ipu)
1257 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1258 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1263 irq = irq_linear_revmap(ipu->domain, i);
1268 irq_domain_remove(ipu->domain);
1271 void ipu_dump(struct ipu_soc *ipu)
1275 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1276 ipu_cm_read(ipu, IPU_CONF));
1277 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1278 ipu_idmac_read(ipu, IDMAC_CONF));
1279 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1280 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1281 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1282 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1283 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1284 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1285 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1286 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1287 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1288 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1289 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1290 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1291 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1292 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1293 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1294 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1295 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1296 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1297 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1298 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1299 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1300 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1301 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1302 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1304 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1305 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1312 struct ipu_soc *ipu;
1334 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1335 if (!ipu)
1338 ipu->id = of_alias_get_id(np, "ipu");
1339 if (ipu->id < 0)
1340 ipu->id = 0;
1342 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") &&
1344 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev,
1345 "fsl,prg", ipu->id);
1346 if (!ipu->prg_priv)
1350 ipu->devtype = devtype;
1351 ipu->ipu_type = devtype->type;
1353 spin_lock_init(&ipu->lock);
1354 mutex_init(&ipu->channel_lock);
1355 INIT_LIST_HEAD(&ipu->channels);
1386 ipu->cm_reg = devm_ioremap(&pdev->dev,
1388 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1392 if (!ipu->cm_reg || !ipu->idmac_reg)
1395 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1396 if (IS_ERR(ipu->clk)) {
1397 ret = PTR_ERR(ipu->clk);
1402 platform_set_drvdata(pdev, ipu);
1404 ret = clk_prepare_enable(ipu->clk);
1410 ipu->dev = &pdev->dev;
1411 ipu->irq_sync = irq_sync;
1412 ipu->irq_err = irq_err;
1419 ret = ipu_memory_reset(ipu);
1423 ret = ipu_irq_init(ipu);
1428 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1431 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1435 ret = ipu_add_client_devices(ipu, ipu_base);
1447 ipu_submodules_exit(ipu);
1449 ipu_irq_exit(ipu);
1452 clk_disable_unprepare(ipu->clk);
1458 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1461 ipu_submodules_exit(ipu);
1462 ipu_irq_exit(ipu);
1464 clk_disable_unprepare(ipu->clk);