Lines Matching defs:vou
123 struct zx_vou_hw *vou;
220 return zcrtc->vou;
227 struct zx_vou_hw *vou = zcrtc->vou;
229 zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud);
235 struct zx_vou_hw *vou = zcrtc->vou;
258 zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
262 zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,
266 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
270 zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,
274 zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);
279 struct zx_vou_hw *vou = crtc_to_vou(crtc);
283 zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);
286 zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
293 struct zx_vou_hw *vou = zcrtc->vou;
298 zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);
338 zx_writel_mask(vou->vouctl + reg, 0x7 << shift,
343 zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,
358 struct zx_vou_hw *vou = zcrtc->vou;
372 zx_writel(vou->timing + regs->fir_active, val);
377 zx_writel(vou->timing + regs->fir_htiming, val);
382 zx_writel(vou->timing + regs->fir_vtiming, val);
388 val = zx_readl(vou->timing + SEC_V_ACTIVE);
391 zx_writel(vou->timing + SEC_V_ACTIVE, val);
400 zx_writel(vou->timing + regs->sec_vtiming, val);
409 zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,
416 zx_writel(vou->timing + regs->timing_shift, val);
417 zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL);
421 zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask,
425 zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
448 DRM_DEV_ERROR(vou->dev, "failed to set pixclk rate: %d\n", ret);
454 DRM_DEV_ERROR(vou->dev, "failed to enable pixclk: %d\n", ret);
462 struct zx_vou_hw *vou = zcrtc->vou;
472 zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);
502 struct zx_vou_hw *vou = crtc_to_vou(crtc);
505 zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask,
514 struct zx_vou_hw *vou = crtc_to_vou(crtc);
516 zx_writel_mask(vou->timing + TIMING_INT_CTRL,
531 static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
534 struct device *dev = vou->dev;
543 zcrtc->vou = vou;
553 zplane->layer = vou->osd + MAIN_GL_OFFSET;
554 zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;
555 zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
556 zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;
558 zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
559 zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
560 zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
564 zplane->layer = vou->osd + AUX_GL_OFFSET;
565 zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;
566 zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
567 zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;
569 zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
570 zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
571 zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
602 vou->main_crtc = zcrtc;
604 vou->aux_crtc = zcrtc;
612 struct zx_vou_hw *vou = zcrtc->vou;
617 zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);
618 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);
620 zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,
622 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,
626 zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);
633 struct zx_vou_hw *vou = zcrtc->vou;
637 zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);
640 static void zx_overlay_init(struct drm_device *drm, struct zx_vou_hw *vou)
642 struct device *dev = vou->dev;
658 zplane->layer = vou->osd + OSD_VL_OFFSET(i);
659 zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i);
660 zplane->rsz = vou->otfppu + RSZ_VL_OFFSET(i);
684 struct zx_vou_hw *vou = dev_id;
688 state = zx_readl(vou->timing + TIMING_INT_STATE);
689 zx_writel(vou->timing + TIMING_INT_STATE, state);
692 drm_crtc_handle_vblank(&vou->main_crtc->crtc);
695 drm_crtc_handle_vblank(&vou->aux_crtc->crtc);
698 state = zx_readl(vou->osd + OSD_INT_STA);
699 zx_writel(vou->osd + OSD_INT_CLRSTA, state);
702 zx_osd_int_update(vou->main_crtc);
705 zx_osd_int_update(vou->aux_crtc);
708 DRM_DEV_ERROR(vou->dev, "OSD ERROR: 0x%08x!\n", state);
713 static void vou_dtrc_init(struct zx_vou_hw *vou)
716 zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,
720 zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,
724 zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,
726 zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,
730 zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) |
734 static void vou_hw_init(struct zx_vou_hw *vou)
737 zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);
740 zx_writel(vou->vouctl + VOU_CLK_EN, ~0);
743 zx_writel(vou->osd + OSD_INT_CLRSTA, ~0);
744 zx_writel(vou->timing + TIMING_INT_STATE, ~0);
747 zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE);
748 zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE);
751 zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a);
757 zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);
759 vou_dtrc_init(vou);
766 struct zx_vou_hw *vou;
771 vou = devm_kzalloc(dev, sizeof(*vou), GFP_KERNEL);
772 if (!vou)
776 vou->osd = devm_ioremap_resource(dev, res);
777 if (IS_ERR(vou->osd)) {
778 ret = PTR_ERR(vou->osd);
784 vou->timing = devm_ioremap_resource(dev, res);
785 if (IS_ERR(vou->timing)) {
786 ret = PTR_ERR(vou->timing);
793 vou->dtrc = devm_ioremap_resource(dev, res);
794 if (IS_ERR(vou->dtrc)) {
795 ret = PTR_ERR(vou->dtrc);
801 vou->vouctl = devm_ioremap_resource(dev, res);
802 if (IS_ERR(vou->vouctl)) {
803 ret = PTR_ERR(vou->vouctl);
810 vou->otfppu = devm_ioremap_resource(dev, res);
811 if (IS_ERR(vou->otfppu)) {
812 ret = PTR_ERR(vou->otfppu);
821 vou->axi_clk = devm_clk_get(dev, "aclk");
822 if (IS_ERR(vou->axi_clk)) {
823 ret = PTR_ERR(vou->axi_clk);
828 vou->ppu_clk = devm_clk_get(dev, "ppu_wclk");
829 if (IS_ERR(vou->ppu_clk)) {
830 ret = PTR_ERR(vou->ppu_clk);
835 ret = clk_prepare_enable(vou->axi_clk);
841 clk_prepare_enable(vou->ppu_clk);
847 vou->dev = dev;
848 dev_set_drvdata(dev, vou);
850 vou_hw_init(vou);
852 ret = devm_request_irq(dev, irq, vou_irq_handler, 0, "zx_vou", vou);
854 DRM_DEV_ERROR(dev, "failed to request vou irq: %d\n", ret);
858 ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN);
865 ret = zx_crtc_init(drm, vou, VOU_CHN_AUX);
872 zx_overlay_init(drm, vou);
877 clk_disable_unprepare(vou->ppu_clk);
879 clk_disable_unprepare(vou->axi_clk);
886 struct zx_vou_hw *vou = dev_get_drvdata(dev);
888 clk_disable_unprepare(vou->axi_clk);
889 clk_disable_unprepare(vou->ppu_clk);