Lines Matching defs:bits
128 const struct zx_crtc_bits *bits;
294 const struct zx_crtc_bits *bits = zcrtc->bits;
307 shift = bits->div_vga_shift;
311 shift = bits->div_pic_shift;
315 shift = bits->div_tvenc_shift;
319 shift = bits->div_hdmi_pnx_shift;
323 shift = bits->div_hdmi_shift;
327 shift = bits->div_inf_shift;
331 shift = bits->div_layer_shift;
337 /* Each divider occupies 3 bits */
360 const struct zx_crtc_bits *bits = zcrtc->bits;
385 u32 shift = bits->sec_vactive_shift;
386 u32 mask = bits->sec_vactive_mask;
409 zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,
410 pol << bits->polarity_shift);
420 scan_mask = bits->interlace_select | bits->pi_enable;
425 zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
426 bits->tc_enable);
461 const struct zx_crtc_bits *bits = zcrtc->bits;
472 zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);
503 u32 int_frame_mask = zcrtc->bits->int_frame_mask;
517 zcrtc->bits->int_frame_mask, 0);
557 zplane->bits = &zx_gl_bits[0];
562 zcrtc->bits = &main_crtc_bits;
568 zplane->bits = &zx_gl_bits[1];
573 zcrtc->bits = &aux_crtc_bits;
614 const struct vou_layer_bits *bits = zplane->bits;
617 zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);
618 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);
620 zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,
621 bits->chnsel);
622 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,
623 bits->clksel);
626 zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);
635 const struct vou_layer_bits *bits = zplane->bits;
637 zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);
661 zplane->bits = &zx_vl_bits[i];