Lines Matching defs:port
540 unsigned int port;
642 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
644 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
645 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
894 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
928 if (dsi->variant->port == 0) {
1077 (dsi->variant->port == 0 ?
1103 if (dsi->variant->port == 0)
1230 if (dsi->variant->port == 0) {
1378 .port = 1,
1397 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1402 * Initial handler for port 1 where we need the reg_dma workaround.
1419 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1447 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1497 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1553 vc4_dsi_encoder->base.type = dsi->variant->port ?