Lines Matching refs:dispc
310 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
312 iowrite32(val, dispc->base_common + reg);
315 static u32 dispc_read(struct dispc_device *dispc, u16 reg)
317 return ioread32(dispc->base_common + reg);
321 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
323 void __iomem *base = dispc->base_vid[hw_plane];
328 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)
330 void __iomem *base = dispc->base_vid[hw_plane];
335 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
338 void __iomem *base = dispc->base_ovr[hw_videoport];
343 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
345 void __iomem *base = dispc->base_ovr[hw_videoport];
350 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
353 void __iomem *base = dispc->base_vp[hw_videoport];
358 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
360 void __iomem *base = dispc->base_vp[hw_videoport];
390 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end)
392 return FLD_GET(dispc_read(dispc, idx), start, end);
395 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
398 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val,
402 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,
405 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);
408 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,
411 dispc_vid_write(dispc, hw_plane, idx,
412 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),
416 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx,
419 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end);
422 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
425 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx),
430 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx,
433 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end);
436 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
439 dispc_ovr_write(dispc, ovr, idx,
440 FLD_MOD(dispc_ovr_read(dispc, ovr, idx),
496 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc,
499 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS);
504 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc,
509 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
512 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc,
515 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);
520 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc,
525 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);
528 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc,
531 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE);
536 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc,
541 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);
544 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc,
547 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);
552 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc,
557 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);
560 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc,
563 dispc_k2g_vp_write_irqstatus(dispc, 0, mask);
564 dispc_k2g_vid_write_irqstatus(dispc, 0, mask);
568 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc)
573 dispc_write(dispc, DISPC_IRQSTATUS,
574 dispc_read(dispc, DISPC_IRQSTATUS));
576 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0);
577 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0);
579 dispc_k2g_clear_irqstatus(dispc, stat);
584 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc)
588 stat |= dispc_k2g_vp_read_irqenable(dispc, 0);
589 stat |= dispc_k2g_vid_read_irqenable(dispc, 0);
595 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
597 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);
600 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
602 dispc_k2g_vp_set_irqenable(dispc, 0, mask);
603 dispc_k2g_vid_set_irqenable(dispc, 0, mask);
605 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));
608 dispc_k2g_read_irqenable(dispc);
611 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc,
614 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport));
619 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
624 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat);
627 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
630 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));
635 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
640 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);
643 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
646 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport));
651 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
656 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat);
659 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
662 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));
667 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
672 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);
676 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
681 for (i = 0; i < dispc->feat->num_vps; ++i) {
683 dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
687 for (i = 0; i < dispc->feat->num_planes; ++i) {
689 dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
693 if (dispc->feat->subrev == DISPC_K2G)
696 dispc_write(dispc, DISPC_IRQSTATUS, top_clear);
699 dispc_read(dispc, DISPC_IRQSTATUS);
703 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
708 for (i = 0; i < dispc->feat->num_vps; ++i)
709 status |= dispc_k3_vp_read_irqstatus(dispc, i);
711 for (i = 0; i < dispc->feat->num_planes; ++i)
712 status |= dispc_k3_vid_read_irqstatus(dispc, i);
714 dispc_k3_clear_irqstatus(dispc, status);
719 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
724 for (i = 0; i < dispc->feat->num_vps; ++i)
725 enable |= dispc_k3_vp_read_irqenable(dispc, i);
727 for (i = 0; i < dispc->feat->num_planes; ++i)
728 enable |= dispc_k3_vid_read_irqenable(dispc, i);
733 static void dispc_k3_set_irqenable(struct dispc_device *dispc,
740 old_mask = dispc_k3_read_irqenable(dispc);
743 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask);
745 for (i = 0; i < dispc->feat->num_vps; ++i) {
746 dispc_k3_vp_set_irqenable(dispc, i, mask);
753 for (i = 0; i < dispc->feat->num_planes; ++i) {
754 dispc_k3_vid_set_irqenable(dispc, i, mask);
762 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable);
765 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
768 dispc_read(dispc, DISPC_IRQENABLE_SET);
771 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
773 switch (dispc->feat->subrev) {
775 return dispc_k2g_read_and_clear_irqstatus(dispc);
778 return dispc_k3_read_and_clear_irqstatus(dispc);
785 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
787 switch (dispc->feat->subrev) {
789 dispc_k2g_set_irqenable(dispc, mask);
793 dispc_k3_set_irqenable(dispc, mask);
823 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc,
837 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
843 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
846 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n",
851 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI &&
853 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n",
854 __func__, dispc->feat->vp_name[hw_videoport]);
861 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power)
865 if (WARN_ON(!dispc->oldi_io_ctrl))
868 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL,
870 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL,
872 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL,
874 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL,
876 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL,
880 static void dispc_set_num_datalines(struct dispc_device *dispc,
903 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
906 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
921 dev_warn(dispc->dev, "%s: %d port width not supported\n",
932 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
934 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
938 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)))
939 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n",
943 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
949 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
955 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
956 dispc_oldi_tx_power(dispc, true);
958 dispc_enable_oldi(dispc, hw_videoport, fmt);
962 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
971 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
977 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
987 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
992 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
1014 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI)
1017 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
1026 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1030 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1033 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
1035 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
1038 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
1040 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
1041 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
1043 dispc_oldi_tx_power(dispc, false);
1047 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
1049 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
1052 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
1054 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
1055 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
1098 static void dispc_vp_set_default_color(struct dispc_device *dispc,
1105 dispc_ovr_write(dispc, hw_videoport,
1107 dispc_ovr_write(dispc, hw_videoport,
1111 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
1119 bus_type = dispc->feat->vp_bus_type[hw_videoport];
1121 max_pclk = dispc->feat->max_pclk_khz[bus_type];
1126 if (mode->clock < dispc->feat->min_pclk_khz)
1170 if (dispc->memory_bandwidth_limit) {
1178 if (dispc->memory_bandwidth_limit < bandwidth)
1185 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport)
1187 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]);
1190 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__,
1196 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
1198 clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
1213 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
1219 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
1221 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n",
1226 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]);
1229 dev_warn(dispc->dev,
1233 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n",
1234 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
1240 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc,
1245 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,
1249 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
1253 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1255 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1257 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1261 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
1265 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1267 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1269 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1273 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
1276 switch (dispc->feat->subrev) {
1278 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
1282 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
1286 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,
1295 void dispc_ovr_enable_layer(struct dispc_device *dispc,
1298 if (dispc->feat->subrev == DISPC_K2G)
1301 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1384 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1399 dev_warn(dispc->dev, "%s: No post offset support for %s\n",
1403 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1407 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1422 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1504 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,
1511 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n",
1516 if (dispc->feat->subrev == DISPC_K2G)
1517 dispc_k2g_vid_write_csc(dispc, hw_plane, coef);
1519 dispc_k3_vid_write_csc(dispc, hw_plane, coef);
1522 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,
1525 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);
1542 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc,
1566 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__);
1574 dispc_vid_write(dispc, hw_plane, reg, c0);
1586 dispc_vid_write(dispc, hw_plane, reg, c12);
1611 static int dispc_vid_calc_scaling(struct dispc_device *dispc,
1616 const struct dispc_features_scaling *f = &dispc->feat->scaling;
1665 dev_dbg(dispc->dev,
1678 dev_dbg(dispc->dev,
1695 dev_dbg(dispc->dev,
1716 dev_dbg(dispc->dev,
1734 dev_dbg(dispc->dev,
1750 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev,
1758 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev,
1765 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc,
1769 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc,
1775 static void dispc_vid_set_scaling(struct dispc_device *dispc,
1781 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1785 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1793 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1798 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
1800 dispc_vid_write_fir_coefs(dispc, hw_plane,
1805 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,
1807 dispc_vid_write_fir_coefs(dispc, hw_plane,
1814 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);
1815 dispc_vid_write_fir_coefs(dispc, hw_plane,
1821 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);
1822 dispc_vid_write_fir_coefs(dispc, hw_plane,
1875 static void dispc_plane_set_pixel_format(struct dispc_device *dispc,
1882 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1892 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len)
1894 WARN_ON(!dispc->fourccs);
1896 *len = dispc->num_fourccs;
1898 return dispc->fourccs;
1914 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
1918 bool lite = dispc->feat->vid_lite[hw_plane];
1928 dev_dbg(dispc->dev,
1938 dev_dbg(dispc->dev,
1945 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false);
1985 int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
1989 bool lite = dispc->feat->vid_lite[hw_plane];
1996 dispc_vid_calc_scaling(dispc, state, &scale, lite);
1998 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
2000 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, paddr & 0xffffffff);
2001 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)paddr >> 32);
2002 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, paddr & 0xffffffff);
2003 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)paddr >> 32);
2005 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
2010 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2013 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2016 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
2026 dispc_vid_write(dispc, hw_plane,
2028 dispc_vid_write(dispc, hw_plane,
2030 dispc_vid_write(dispc, hw_plane,
2032 dispc_vid_write(dispc, hw_plane,
2035 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,
2042 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,
2046 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);
2051 dispc_vid_csc_setup(dispc, hw_plane, state);
2052 dispc_vid_csc_enable(dispc, hw_plane, true);
2054 dispc_vid_csc_enable(dispc, hw_plane, false);
2057 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
2061 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2064 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2070 int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)
2072 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
2077 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
2079 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);
2082 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc,
2085 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,
2089 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc,
2092 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,
2096 static void dispc_k2g_plane_init(struct dispc_device *dispc)
2100 dev_dbg(dispc->dev, "%s()\n", __func__);
2103 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2105 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2107 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2108 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2121 dev_dbg(dispc->dev,
2123 dispc->feat->vid_name[hw_plane],
2129 dispc_vid_set_buf_threshold(dispc, hw_plane,
2131 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2134 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2141 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2146 static void dispc_k3_plane_init(struct dispc_device *dispc)
2152 dev_dbg(dispc->dev, "%s()\n", __func__);
2154 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
2155 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
2158 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2160 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2162 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2163 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2176 dev_dbg(dispc->dev,
2178 dispc->feat->vid_name[hw_plane],
2184 dispc_vid_set_buf_threshold(dispc, hw_plane,
2186 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2189 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2192 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2197 static void dispc_plane_init(struct dispc_device *dispc)
2199 switch (dispc->feat->subrev) {
2201 dispc_k2g_plane_init(dispc);
2205 dispc_k3_plane_init(dispc);
2212 static void dispc_vp_init(struct dispc_device *dispc)
2216 dev_dbg(dispc->dev, "%s()\n", __func__);
2219 for (i = 0; i < dispc->feat->num_vps; i++)
2220 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
2223 static void dispc_initial_config(struct dispc_device *dispc)
2225 dispc_plane_init(dispc);
2226 dispc_vp_init(dispc);
2229 if (dispc->feat->subrev == DISPC_J721E) {
2230 dispc_write(dispc, DISPC_CONNECTIONS,
2237 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc,
2240 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2241 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2244 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2246 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2254 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
2259 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc,
2262 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2263 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2266 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2268 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2276 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2280 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc,
2283 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2284 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2287 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2289 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT))
2298 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2302 static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
2305 switch (dispc->feat->subrev) {
2307 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
2310 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
2313 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport);
2326 static void dispc_vp_set_gamma(struct dispc_device *dispc,
2331 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2332 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2336 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n",
2339 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT)
2373 dispc_vp_write_gamma_table(dispc, hw_videoport);
2420 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2433 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
2437 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2446 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
2450 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2485 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2499 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
2503 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2512 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
2516 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2520 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
2537 dispc_vp_set_gamma(dispc, hw_videoport, lut, length);
2542 if (dispc->feat->subrev == DISPC_K2G)
2543 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
2545 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
2548 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
2551 dispc_vp_set_default_color(dispc, hw_videoport, 0);
2552 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset);
2555 int dispc_runtime_suspend(struct dispc_device *dispc)
2557 dev_dbg(dispc->dev, "suspend\n");
2559 dispc->is_enabled = false;
2561 clk_disable_unprepare(dispc->fclk);
2566 int dispc_runtime_resume(struct dispc_device *dispc)
2568 dev_dbg(dispc->dev, "resume\n");
2570 clk_prepare_enable(dispc->fclk);
2572 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0)
2573 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n");
2575 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n",
2576 dispc_read(dispc, DSS_REVISION));
2578 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n",
2579 REG_GET(dispc, DSS_SYSSTATUS, 1, 1),
2580 REG_GET(dispc, DSS_SYSSTATUS, 2, 2),
2581 REG_GET(dispc, DSS_SYSSTATUS, 3, 3));
2583 if (dispc->feat->subrev == DISPC_AM65X)
2584 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n",
2585 REG_GET(dispc, DSS_SYSSTATUS, 5, 5),
2586 REG_GET(dispc, DSS_SYSSTATUS, 6, 6),
2587 REG_GET(dispc, DSS_SYSSTATUS, 7, 7));
2589 dev_dbg(dispc->dev, "DISPC IDLE %d\n",
2590 REG_GET(dispc, DSS_SYSSTATUS, 9, 9));
2592 dispc_initial_config(dispc);
2594 dispc->is_enabled = true;
2596 tidss_irq_resume(dispc->tidss);
2605 tidss->dispc = NULL;
2632 struct dispc_device *dispc)
2634 dispc->oldi_io_ctrl =
2637 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) {
2638 dispc->oldi_io_ctrl = NULL;
2639 } else if (IS_ERR(dispc->oldi_io_ctrl)) {
2641 __func__, PTR_ERR(dispc->oldi_io_ctrl));
2642 return PTR_ERR(dispc->oldi_io_ctrl);
2647 static void dispc_init_errata(struct dispc_device *dispc)
2655 dispc->errata.i2000 = true;
2656 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n");
2664 struct dispc_device *dispc;
2679 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL);
2680 if (!dispc)
2683 dispc->tidss = tidss;
2684 dispc->dev = dev;
2685 dispc->feat = feat;
2687 dispc_init_errata(dispc);
2689 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
2690 sizeof(*dispc->fourccs), GFP_KERNEL);
2691 if (!dispc->fourccs)
2696 if (dispc->errata.i2000 &&
2700 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc;
2703 dispc->num_fourccs = num_fourccs;
2705 dispc_common_regmap = dispc->feat->common_regs;
2707 r = dispc_iomap_resource(pdev, dispc->feat->common,
2708 &dispc->base_common);
2712 for (i = 0; i < dispc->feat->num_planes; i++) {
2713 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
2714 &dispc->base_vid[i]);
2719 for (i = 0; i < dispc->feat->num_vps; i++) {
2720 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
2724 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i],
2725 &dispc->base_ovr[i]);
2729 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i],
2730 &dispc->base_vp[i]);
2734 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]);
2737 dispc->feat->vpclk_name[i], PTR_ERR(clk));
2740 dispc->vp_clk[i] = clk;
2747 dispc->vp_data[i].gamma_table = gamma_table;
2751 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc);
2756 dispc->fclk = devm_clk_get(dev, "fck");
2757 if (IS_ERR(dispc->fclk)) {
2759 __func__, PTR_ERR(dispc->fclk));
2760 return PTR_ERR(dispc->fclk);
2762 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk));
2764 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
2765 &dispc->memory_bandwidth_limit);
2767 tidss->dispc = dispc;