Lines Matching refs:value
486 u32 value = readl(sor->regs + (offset << 2));
488 trace_sor_readl(sor->dev, offset, value);
490 return value;
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
496 trace_sor_writel(sor->dev, offset, value);
497 writel(value, sor->regs + (offset << 2));
544 u32 value;
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
569 u32 value;
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
573 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
646 u32 value;
652 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
655 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
658 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
662 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
664 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
671 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
674 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
676 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
681 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
682 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
688 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
697 u32 value;
700 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
701 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
706 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
708 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
713 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
714 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
720 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
728 u32 value;
731 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
734 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
737 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
741 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
743 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
746 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
748 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
750 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
755 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
762 u32 mask = 0x08, adj = 0, value;
765 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
766 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
767 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
770 value |= SOR_PLL1_TMDS_TERM;
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
776 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
777 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
778 value |= SOR_PLL1_TMDS_TERMADJ(adj);
779 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
783 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
784 if (value & SOR_PLL1_TERM_COMPOUT)
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
791 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
792 value |= SOR_PLL1_TMDS_TERMADJ(adj);
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
796 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
797 value |= SOR_DP_PADCTL_PAD_CAL_PD;
798 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
806 u32 pattern = 0, tx_pu = 0, value;
809 for (value = 0, i = 0; i < link->lanes; i++) {
824 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
829 value = SOR_DP_TPG_SCRAMBLER_NONE |
834 value = SOR_DP_TPG_SCRAMBLER_NONE |
839 value = SOR_DP_TPG_SCRAMBLER_NONE |
848 value |= SOR_DP_TPG_CHANNEL_CODING;
850 pattern = pattern << 8 | value;
861 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
862 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
863 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
864 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
865 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
876 u32 value;
883 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
884 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
885 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
886 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
888 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
889 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
890 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
893 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
895 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
901 value &= ~SOR_PLL1_LOADADJ_MASK;
905 value |= SOR_PLL1_LOADADJ(0x3);
909 value |= SOR_PLL1_LOADADJ(0x4);
913 value |= SOR_PLL1_LOADADJ(0x6);
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
920 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
923 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
925 value |= SOR_DP_SPARE_PANEL_INTERNAL;
927 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
969 u32 value;
971 value = tegra_sor_readl(sor, SOR_PWM_DIV);
972 value &= ~SOR_PWM_DIV_MASK;
973 value |= 0x400; /* period */
974 tegra_sor_writel(sor, value, SOR_PWM_DIV);
976 value = tegra_sor_readl(sor, SOR_PWM_CTL);
977 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
978 value |= 0x400; /* duty cycle */
979 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
980 value |= SOR_PWM_CTL_TRIGGER;
981 tegra_sor_writel(sor, value, SOR_PWM_CTL);
986 value = tegra_sor_readl(sor, SOR_PWM_CTL);
987 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
998 unsigned long value, timeout;
1001 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1002 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1003 value |= SOR_SUPER_STATE_MODE_NORMAL;
1004 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1008 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1009 value |= SOR_SUPER_STATE_ATTACHED;
1010 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1016 value = tegra_sor_readl(sor, SOR_TEST);
1017 if ((value & SOR_TEST_ATTACHED) != 0)
1028 unsigned long value, timeout;
1034 value = tegra_sor_readl(sor, SOR_TEST);
1035 value &= SOR_TEST_HEAD_MODE_MASK;
1037 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1048 u32 value;
1050 value = tegra_sor_readl(sor, SOR_PWR);
1051 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1052 tegra_sor_writel(sor, value, SOR_PWR);
1057 value = tegra_sor_readl(sor, SOR_PWR);
1058 if ((value & SOR_PWR_TRIGGER) == 0)
1245 u32 value;
1247 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1248 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1249 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1250 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1252 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1253 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1254 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1256 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1257 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1259 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1265 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1267 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1268 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1269 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1271 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1272 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1273 value |= config->hblank_symbols & 0xffff;
1274 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1276 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1277 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1278 value |= config->vblank_symbols & 0xffff;
1279 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1288 u32 value;
1290 value = tegra_sor_readl(sor, SOR_STATE1);
1291 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1292 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1293 value &= ~SOR_STATE_ASY_OWNER_MASK;
1295 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1299 value &= ~SOR_STATE_ASY_HSYNCPOL;
1302 value |= SOR_STATE_ASY_HSYNCPOL;
1305 value &= ~SOR_STATE_ASY_VSYNCPOL;
1308 value |= SOR_STATE_ASY_VSYNCPOL;
1312 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1316 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1320 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1324 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1328 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1332 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1336 tegra_sor_writel(sor, value, SOR_STATE1);
1343 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1344 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1350 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1351 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1357 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1358 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1364 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1365 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1373 unsigned long value, timeout;
1376 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1377 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1378 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1384 value = tegra_sor_readl(sor, SOR_PWR);
1385 if (value & SOR_PWR_MODE_SAFE)
1389 if ((value & SOR_PWR_MODE_SAFE) == 0)
1393 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1394 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1395 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1399 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1400 value &= ~SOR_SUPER_STATE_ATTACHED;
1401 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1407 value = tegra_sor_readl(sor, SOR_TEST);
1408 if ((value & SOR_TEST_ATTACHED) == 0)
1414 if ((value & SOR_TEST_ATTACHED) != 0)
1422 unsigned long value, timeout;
1425 value = tegra_sor_readl(sor, SOR_PWR);
1426 value &= ~SOR_PWR_NORMAL_STATE_PU;
1427 value |= SOR_PWR_TRIGGER;
1428 tegra_sor_writel(sor, value, SOR_PWR);
1433 value = tegra_sor_readl(sor, SOR_PWR);
1434 if ((value & SOR_PWR_TRIGGER) == 0)
1440 if ((value & SOR_PWR_TRIGGER) != 0)
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1451 value |= SOR_PLL2_PORT_POWERDOWN;
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1457 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1461 value |= SOR_PLL2_SEQ_PLLCAPPD;
1462 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1472 u32 value;
1477 value = tegra_sor_readl(sor, SOR_CRCA);
1478 if (value & SOR_CRCA_VALID)
1494 u32 value;
1503 value = tegra_sor_readl(sor, SOR_STATE1);
1504 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1505 tegra_sor_writel(sor, value, SOR_STATE1);
1507 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1508 value |= SOR_CRC_CNTRL_ENABLE;
1509 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1511 value = tegra_sor_readl(sor, SOR_TEST);
1512 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1513 tegra_sor_writel(sor, value, SOR_TEST);
1520 value = tegra_sor_readl(sor, SOR_CRCB);
1522 seq_printf(s, "%08x\n", value);
1849 u32 value = 0;
1853 value = (value << 8) | ptr[i - 1];
1855 return value;
1864 u32 value;
1885 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1888 tegra_sor_writel(sor, value, offset);
1899 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1900 tegra_sor_writel(sor, value, offset++);
1904 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1905 tegra_sor_writel(sor, value, offset++);
1915 u32 value;
1919 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1920 value &= ~INFOFRAME_CTRL_SINGLE;
1921 value &= ~INFOFRAME_CTRL_OTHER;
1922 value &= ~INFOFRAME_CTRL_ENABLE;
1923 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1941 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1942 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1943 value |= INFOFRAME_CTRL_ENABLE;
1944 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1969 u32 value;
1976 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1977 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1978 tegra_sor_writel(sor, value, SOR_INT_MASK);
1982 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1983 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1995 u32 value;
1997 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2000 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2001 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2005 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2007 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2009 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2011 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2021 u32 value;
2040 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2041 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2042 value |= INFOFRAME_CTRL_ENABLE;
2043 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2050 u32 value;
2056 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2059 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2062 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2063 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2066 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2070 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2071 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2073 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2074 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2086 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2087 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2090 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2094 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2098 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2099 value &= ~SOR_HDMI_AUDIO_N_RESET;
2100 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2107 u32 value;
2109 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2110 value &= ~INFOFRAME_CTRL_ENABLE;
2111 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2133 u32 value;
2135 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2136 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2137 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2138 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2161 u32 value;
2163 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2164 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2165 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2166 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2211 u32 value;
2225 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2228 value &= ~SOR1_TIMING_CYA;
2230 value &= ~SOR_ENABLE(sor->index);
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2258 u32 value;
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2287 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2293 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2297 value &= ~SOR_PLL0_VCOPD;
2298 value &= ~SOR_PLL0_PWR;
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2302 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2308 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2309 value &= ~SOR_PLL2_PORT_POWERDOWN;
2310 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2314 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2315 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2317 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2320 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2321 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2327 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2329 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2332 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2333 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2339 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2340 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2341 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2345 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2348 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2351 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2352 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2357 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2358 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2359 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2360 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2362 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2363 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2364 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2365 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2366 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2367 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2369 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2371 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2373 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2376 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2380 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2381 tegra_sor_writel(sor, value, SOR_REFCLK);
2385 for (value = 0, i = 0; i < 5; i++)
2386 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2390 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2434 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2438 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2440 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2445 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2447 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2455 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2457 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2459 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2462 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2463 value |= H_PULSE2_ENABLE;
2464 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2476 value = tegra_sor_readl(sor, SOR_STATE1);
2477 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2478 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2479 tegra_sor_writel(sor, value, SOR_STATE1);
2482 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2483 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2495 value &= ~SOR_PLL0_ICHPMP_MASK;
2496 value &= ~SOR_PLL0_FILTER_MASK;
2497 value &= ~SOR_PLL0_VCOCAP_MASK;
2498 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2499 value |= SOR_PLL0_FILTER(settings->filter);
2500 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2504 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2505 value &= ~SOR_PLL1_LOADADJ_MASK;
2506 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2507 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2508 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2509 value |= SOR_PLL1_TMDS_TERM;
2510 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2513 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2514 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2515 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2516 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2517 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2518 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2519 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2520 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2523 value = settings->drive_current[3] << 24 |
2527 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2529 value = settings->preemphasis[3] << 24 |
2533 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2535 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2536 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2537 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2538 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2539 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2541 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2542 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2543 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2544 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2547 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2548 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2553 value = VSYNC_H_POSITION(1);
2554 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2557 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2558 value &= ~DITHER_CONTROL_MASK;
2559 value &= ~BASE_COLOR_SIZE_MASK;
2563 value |= BASE_COLOR_SIZE_666;
2567 value |= BASE_COLOR_SIZE_888;
2571 value |= BASE_COLOR_SIZE_101010;
2575 value |= BASE_COLOR_SIZE_121212;
2580 value |= BASE_COLOR_SIZE_888;
2584 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2587 value = tegra_sor_readl(sor, SOR_STATE1);
2588 value &= ~SOR_STATE_ASY_OWNER_MASK;
2589 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2590 tegra_sor_writel(sor, value, SOR_STATE1);
2597 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2598 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2599 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2600 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2603 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2604 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2605 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2606 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2613 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2614 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2615 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2622 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2625 value |= SOR1_TIMING_CYA;
2627 value |= SOR_ENABLE(sor->index);
2629 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2632 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2633 value &= ~PROTOCOL_MASK;
2634 value |= PROTOCOL_SINGLE_TMDS_A;
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2659 u32 value;
2683 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2684 value &= ~SOR_ENABLE(sor->index);
2685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2688 value = tegra_sor_readl(sor, SOR_STATE1);
2689 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2690 value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2691 value &= ~SOR_STATE_ASY_OWNER_MASK;
2692 tegra_sor_writel(sor, value, SOR_STATE1);
2728 u32 value;
2769 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2770 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2771 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2776 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2780 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2784 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2785 value |= SOR_PLL2_SEQ_PLLCAPPD;
2786 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2790 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2791 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2792 value &= ~SOR_PLL2_PORT_POWERDOWN;
2793 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2795 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2796 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2799 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2801 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2803 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2807 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2810 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2812 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2814 value |= SOR_DP_SPARE_SEQ_ENABLE;
2815 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2821 value &= ~SOR_PLL0_ICHPMP_MASK;
2822 value &= ~SOR_PLL0_VCOCAP_MASK;
2823 value |= SOR_PLL0_ICHPMP(0x1);
2824 value |= SOR_PLL0_VCOCAP(0x3);
2825 value |= SOR_PLL0_RESISTOR_EXT;
2826 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2829 for (value = 0, i = 0; i < 5; i++)
2830 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2834 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2868 value = tegra_sor_readl(sor, SOR_STATE1);
2869 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2870 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2871 tegra_sor_writel(sor, value, SOR_STATE1);
2874 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2875 value |= SOR_DP_LINKCTL_ENABLE;
2876 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2903 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2905 tegra_sor_writel(sor, value, SOR_CSTM);
2924 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2925 value |= SOR_ENABLE(sor->index);
2926 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
3652 u32 value;
3656 err = of_property_read_u32(np, "nvidia,interface", &value);
3660 sor->index = value;
3691 u32 value;
3693 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3694 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3696 if (value & SOR_INT_CODEC_SCRATCH0) {
3697 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3699 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3702 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;