Lines Matching defs:output
406 struct tegra_output output;
479 static inline struct tegra_sor *to_sor(struct tegra_output *output)
481 return container_of(output, struct tegra_sor, output);
1070 /* ratio between input and output */
1157 u64 input, output, watermark, num;
1166 output = link_rate * 8 * link->lanes;
1168 if (input >= output)
1172 params.ratio = div64_u64(input * f, output);
1286 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1491 struct drm_crtc *crtc = sor->output.encoder.crtc;
1653 struct drm_crtc *crtc = sor->output.encoder.crtc;
1684 struct tegra_output *output = connector_to_output(connector);
1688 struct tegra_sor *sor = to_sor(output);
1705 struct tegra_output *output = connector_to_output(connector);
1707 struct tegra_sor *sor = to_sor(output);
1734 struct tegra_output *output = connector_to_output(connector);
1735 struct tegra_sor *sor = to_sor(output);
1771 struct tegra_output *output = connector_to_output(connector);
1772 struct tegra_sor *sor = to_sor(output);
1803 struct tegra_output *output = encoder_to_output(encoder);
1807 struct tegra_sor *sor = to_sor(output);
1811 info = &output->connector.display_info;
1828 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1926 &sor->output.connector, mode);
1951 size_t length = drm_eld_size(sor->output.connector.eld), i;
1954 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2143 struct i2c_adapter *ddc = sor->output.ddc;
2171 struct i2c_adapter *ddc = sor->output.ddc;
2182 struct i2c_adapter *ddc = sor->output.ddc;
2194 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2197 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2208 struct tegra_output *output = encoder_to_output(encoder);
2210 struct tegra_sor *sor = to_sor(output);
2249 struct tegra_output *output = encoder_to_output(encoder);
2253 struct tegra_sor *sor = to_sor(output);
2261 state = to_sor_state(output->connector.state);
2415 /* switch the output clock to the parent pixel clock */
2418 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2596 /* configure dynamic range of output */
2656 struct tegra_output *output = encoder_to_output(encoder);
2658 struct tegra_sor *sor = to_sor(output);
2662 if (output->panel)
2663 drm_panel_disable(output->panel);
2669 if (output->connector.status != connector_status_disconnected) {
2712 if (output->panel)
2713 drm_panel_unprepare(output->panel);
2720 struct tegra_output *output = encoder_to_output(encoder);
2722 struct tegra_sor *sor = to_sor(output);
2731 state = to_sor_state(output->connector.state);
2733 info = &output->connector.display_info;
2766 if (output->panel)
2767 drm_panel_prepare(output->panel);
2798 if (output->panel)
2809 if (output->panel)
2859 /* switch the output clock to the parent pixel clock */
2862 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2901 if (output->panel) {
2934 if (output->panel)
2935 drm_panel_enable(output->panel);
3066 if (sor->output.panel) {
3080 sor->output.dev = sor->dev;
3082 drm_connector_init_with_ddc(drm, &sor->output.connector,
3085 sor->output.ddc);
3086 drm_connector_helper_add(&sor->output.connector,
3088 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3090 drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3091 drm_encoder_helper_add(&sor->output.encoder, helpers);
3093 drm_connector_attach_encoder(&sor->output.connector,
3094 &sor->output.encoder);
3095 drm_connector_register(&sor->output.connector);
3097 err = tegra_output_init(drm, &sor->output);
3099 dev_err(client->dev, "failed to initialize output: %d\n", err);
3103 tegra_output_find_possible_crtcs(&sor->output, drm);
3106 err = drm_dp_aux_attach(sor->aux, &sor->output);
3187 tegra_output_exit(&sor->output);
3729 sor->output.dev = sor->dev = &pdev->dev;
3750 sor->output.ddc = &sor->aux->ddc;
3783 err = tegra_output_probe(&sor->output);
3786 "failed to probe output\n");
3894 * the pad output clock, so we have to look it up from device tree.
3904 * If the pad output clock is not available, then we assume
3931 * pad output clock.
3973 tegra_output_remove(&sor->output);
3991 tegra_output_remove(&sor->output);
4001 err = tegra_output_suspend(&sor->output);
4003 dev_err(dev, "failed to suspend output: %d\n", err);
4010 tegra_output_resume(&sor->output);
4029 err = tegra_output_resume(&sor->output);
4031 dev_err(dev, "failed to resume output: %d\n", err);