Lines Matching refs:state
50 to_dsi_state(struct drm_connector_state *state)
52 return container_of(state, struct tegra_dsi_state, base);
104 return to_dsi_state(dsi->output.connector.state);
210 if (!crtc || !crtc->state->active) {
482 struct tegra_dsi_state *state;
486 /* XXX: pass in state into this function? */
488 state = tegra_dsi_get_state(dsi->master);
490 state = tegra_dsi_get_state(dsi);
492 mul = state->mul;
493 div = state->div;
507 DSI_CONTROL_FORMAT(state->format) |
592 unsigned int lanes = state->lanes;
772 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
774 if (!state)
777 if (connector->state) {
778 __drm_atomic_helper_connector_destroy_state(connector->state);
779 kfree(connector->state);
782 __drm_atomic_helper_connector_reset(connector, &state->base);
788 struct tegra_dsi_state *state = to_dsi_state(connector->state);
791 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
907 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
911 struct tegra_dsi_state *state;
921 state = tegra_dsi_get_state(dsi);
923 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
929 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
956 struct tegra_dsi_state *state = to_dsi_state(conn_state);
963 state->pclk = crtc_state->mode.clock * 1000;
965 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
969 state->lanes = tegra_dsi_get_lanes(dsi);
971 err = tegra_dsi_get_format(dsi->format, &state->format);
975 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
978 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
980 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
981 state->lanes);
982 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
983 state->vrefresh);
984 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
989 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
990 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
992 err = mipi_dphy_timing_get_default(&state->timing, state->period);
996 err = mipi_dphy_timing_validate(&state->timing, state->period);
1019 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1024 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);