Lines Matching refs:dsi
29 #include "dsi.h"
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
104 return to_dsi_state(dsi->output.connector.state);
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
109 u32 value = readl(dsi->regs + (offset << 2));
111 trace_dsi_readl(dsi->dev, offset, value);
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
119 trace_dsi_writel(dsi->dev, offset, value);
120 writel(value, dsi->regs + (offset << 2));
202 struct tegra_dsi *dsi = node->info_ent->data;
203 struct drm_crtc *crtc = dsi->output.encoder.crtc;
219 offset, tegra_dsi_readl(dsi, offset));
237 struct tegra_dsi *dsi = to_dsi(output);
239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
241 if (!dsi->debugfs_files)
245 dsi->debugfs_files[i].data = dsi;
247 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
256 struct tegra_dsi *dsi = to_dsi(output);
258 drm_debugfs_remove_files(dsi->debugfs_files, count,
260 kfree(dsi->debugfs_files);
261 dsi->debugfs_files = NULL;
357 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
385 if (dsi->slave)
386 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
443 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
448 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
449 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
455 static void tegra_dsi_enable(struct tegra_dsi *dsi)
459 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
463 if (dsi->slave)
464 tegra_dsi_enable(dsi->slave);
467 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
469 if (dsi->master)
470 return dsi->master->lanes + dsi->lanes;
472 if (dsi->slave)
473 return dsi->lanes + dsi->slave->lanes;
475 return dsi->lanes;
478 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
487 if (dsi->master)
488 state = tegra_dsi_get_state(dsi->master);
490 state = tegra_dsi_get_state(dsi);
495 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
498 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
508 DSI_CONTROL_LANES(dsi->lanes - 1) |
510 tegra_dsi_writel(dsi, value, DSI_CONTROL);
512 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
517 value = tegra_dsi_readl(dsi, DSI_CONTROL);
519 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
525 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
532 tegra_dsi_writel(dsi, value, DSI_CONTROL);
535 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
537 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
547 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
559 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
560 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
561 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
570 if (dsi->master || dsi->slave) {
580 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
581 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
590 if (dsi->master || dsi->slave) {
608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
611 if (dsi->slave) {
612 tegra_dsi_configure(dsi->slave, pipe, mode);
618 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
619 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
624 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
631 value = tegra_dsi_readl(dsi, DSI_STATUS);
641 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
645 value = tegra_dsi_readl(dsi, DSI_CONTROL);
647 tegra_dsi_writel(dsi, value, DSI_CONTROL);
649 if (dsi->slave)
650 tegra_dsi_video_disable(dsi->slave);
653 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
655 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
656 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
660 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
670 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
679 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
686 tegra_dsi_pad_enable(dsi);
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
697 err = tegra_mipi_start_calibration(dsi->mipi);
701 return tegra_mipi_finish_calibration(dsi->mipi);
704 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
718 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
721 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
723 if (dsi->slave)
724 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
727 static void tegra_dsi_disable(struct tegra_dsi *dsi)
731 if (dsi->slave) {
732 tegra_dsi_ganged_disable(dsi->slave);
733 tegra_dsi_ganged_disable(dsi);
736 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
738 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
740 if (dsi->slave)
741 tegra_dsi_disable(dsi->slave);
746 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
750 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
752 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
756 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
758 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
762 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
764 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
766 if (dsi->slave)
767 tegra_dsi_soft_reset(dsi->slave);
824 static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
828 if (dsi->slave)
829 tegra_dsi_unprepare(dsi->slave);
831 err = tegra_mipi_disable(dsi->mipi);
833 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
836 err = host1x_client_suspend(&dsi->client);
838 dev_err(dsi->dev, "failed to suspend: %d\n", err);
845 struct tegra_dsi *dsi = to_dsi(output);
852 tegra_dsi_video_disable(dsi);
866 err = tegra_dsi_wait_idle(dsi, 100);
868 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
870 tegra_dsi_soft_reset(dsi);
875 tegra_dsi_disable(dsi);
877 tegra_dsi_unprepare(dsi);
880 static int tegra_dsi_prepare(struct tegra_dsi *dsi)
884 err = host1x_client_resume(&dsi->client);
886 dev_err(dsi->dev, "failed to resume: %d\n", err);
890 err = tegra_mipi_enable(dsi->mipi);
892 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
895 err = tegra_dsi_pad_calibrate(dsi);
897 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
899 if (dsi->slave)
900 tegra_dsi_prepare(dsi->slave);
910 struct tegra_dsi *dsi = to_dsi(output);
915 err = tegra_dsi_prepare(dsi);
917 dev_err(dsi->dev, "failed to prepare: %d\n", err);
921 state = tegra_dsi_get_state(dsi);
923 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
929 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
934 tegra_dsi_configure(dsi, dc->pipe, mode);
944 tegra_dsi_enable(dsi);
958 struct tegra_dsi *dsi = to_dsi(output);
965 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
969 state->lanes = tegra_dsi_get_lanes(dsi);
971 err = tegra_dsi_get_format(dsi->format, &state->format);
998 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1021 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1040 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1044 if (!dsi->master) {
1045 dsi->output.dev = client->dev;
1047 drm_connector_init(drm, &dsi->output.connector,
1050 drm_connector_helper_add(&dsi->output.connector,
1052 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1054 drm_simple_encoder_init(drm, &dsi->output.encoder,
1056 drm_encoder_helper_add(&dsi->output.encoder,
1059 drm_connector_attach_encoder(&dsi->output.connector,
1060 &dsi->output.encoder);
1061 drm_connector_register(&dsi->output.connector);
1063 err = tegra_output_init(drm, &dsi->output);
1065 dev_err(dsi->dev, "failed to initialize output: %d\n",
1068 dsi->output.encoder.possible_crtcs = 0x3;
1076 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1078 tegra_output_exit(&dsi->output);
1085 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1089 if (dsi->rst) {
1090 err = reset_control_assert(dsi->rst);
1099 clk_disable_unprepare(dsi->clk_lp);
1100 clk_disable_unprepare(dsi->clk);
1102 regulator_disable(dsi->vdd);
1110 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1120 err = regulator_enable(dsi->vdd);
1126 err = clk_prepare_enable(dsi->clk);
1132 err = clk_prepare_enable(dsi->clk_lp);
1140 if (dsi->rst) {
1141 err = reset_control_deassert(dsi->rst);
1151 clk_disable_unprepare(dsi->clk_lp);
1153 clk_disable_unprepare(dsi->clk);
1155 regulator_disable(dsi->vdd);
1168 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1173 parent = clk_get_parent(dsi->clk);
1177 err = clk_set_parent(parent, dsi->clk_parent);
1203 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1214 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1219 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1223 dev_dbg(dsi->dev, " %2u: %s\n", i,
1247 dev_err(dsi->dev, "unhandled response type: %02x\n",
1258 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1268 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1270 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1275 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1286 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1292 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1305 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1318 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1325 struct tegra_dsi *dsi = host_to_tegra(host);
1339 if (packet.size > dsi->video_fifo_depth * 4)
1343 value = tegra_dsi_readl(dsi, DSI_STATUS);
1346 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1350 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1352 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1366 if (packet.size > dsi->host_fifo_depth * 4)
1369 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1377 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1379 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1383 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1387 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1391 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1394 err = tegra_dsi_transmit(dsi, 250);
1400 err = tegra_dsi_wait_for_response(dsi, 250);
1406 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1410 dev_dbg(dsi->dev, "ACK\n");
1416 dev_dbg(dsi->dev, "ESCAPE\n");
1421 dev_err(dsi->dev, "unknown status: %08x\n", value);
1426 err = tegra_dsi_read_response(dsi, msg, count);
1428 dev_err(dsi->dev,
1450 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1456 parent = clk_get_parent(dsi->slave->clk);
1460 err = clk_set_parent(parent, dsi->clk_parent);
1470 struct tegra_dsi *dsi = host_to_tegra(host);
1472 dsi->flags = device->mode_flags;
1473 dsi->format = device->format;
1474 dsi->lanes = device->lanes;
1476 if (dsi->slave) {
1479 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1482 err = tegra_dsi_ganged_setup(dsi);
1484 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1494 if (!dsi->master) {
1495 struct tegra_output *output = &dsi->output;
1511 struct tegra_dsi *dsi = host_to_tegra(host);
1512 struct tegra_output *output = &dsi->output;
1530 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1534 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1538 dsi->slave = platform_get_drvdata(gangster);
1541 if (!dsi->slave) {
1546 dsi->slave->master = dsi;
1554 struct tegra_dsi *dsi;
1558 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1559 if (!dsi)
1562 dsi->output.dev = dsi->dev = &pdev->dev;
1563 dsi->video_fifo_depth = 1920;
1564 dsi->host_fifo_depth = 64;
1566 err = tegra_dsi_ganged_probe(dsi);
1570 err = tegra_output_probe(&dsi->output);
1574 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1581 dsi->flags = MIPI_DSI_MODE_VIDEO;
1582 dsi->format = MIPI_DSI_FMT_RGB888;
1583 dsi->lanes = 4;
1586 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1587 if (IS_ERR(dsi->rst))
1588 return PTR_ERR(dsi->rst);
1591 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1592 if (IS_ERR(dsi->clk)) {
1594 return PTR_ERR(dsi->clk);
1597 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1598 if (IS_ERR(dsi->clk_lp)) {
1600 return PTR_ERR(dsi->clk_lp);
1603 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1604 if (IS_ERR(dsi->clk_parent)) {
1606 return PTR_ERR(dsi->clk_parent);
1609 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1610 if (IS_ERR(dsi->vdd)) {
1612 return PTR_ERR(dsi->vdd);
1615 err = tegra_dsi_setup_clocks(dsi);
1622 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1623 if (IS_ERR(dsi->regs))
1624 return PTR_ERR(dsi->regs);
1626 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
1627 if (IS_ERR(dsi->mipi))
1628 return PTR_ERR(dsi->mipi);
1630 dsi->host.ops = &tegra_dsi_host_ops;
1631 dsi->host.dev = &pdev->dev;
1633 err = mipi_dsi_host_register(&dsi->host);
1639 platform_set_drvdata(pdev, dsi);
1642 INIT_LIST_HEAD(&dsi->client.list);
1643 dsi->client.ops = &dsi_client_ops;
1644 dsi->client.dev = &pdev->dev;
1646 err = host1x_client_register(&dsi->client);
1656 mipi_dsi_host_unregister(&dsi->host);
1658 tegra_mipi_free(dsi->mipi);
1664 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1669 err = host1x_client_unregister(&dsi->client);
1676 tegra_output_remove(&dsi->output);
1678 mipi_dsi_host_unregister(&dsi->host);
1679 tegra_mipi_free(dsi->mipi);
1685 { .compatible = "nvidia,tegra210-dsi", },
1686 { .compatible = "nvidia,tegra132-dsi", },
1687 { .compatible = "nvidia,tegra124-dsi", },
1688 { .compatible = "nvidia,tegra114-dsi", },
1695 .name = "tegra-dsi",