Lines Matching defs:dpaux
25 #include "dpaux.h"
75 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
78 u32 value = readl(dpaux->regs + (offset << 2));
80 trace_dpaux_readl(dpaux->dev, offset, value);
85 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
88 trace_dpaux_writel(dpaux->dev, offset, value);
89 writel(value, dpaux->regs + (offset << 2));
92 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
104 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
108 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
117 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
128 struct tegra_dpaux *dpaux = to_dpaux(aux);
195 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
199 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
204 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
206 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
208 status = wait_for_completion_timeout(&dpaux->complete, timeout);
213 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
214 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
260 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
273 struct tegra_dpaux *dpaux = work_to_dpaux(work);
275 if (dpaux->output)
276 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
281 struct tegra_dpaux *dpaux = data;
286 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
287 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
290 schedule_work(&dpaux->work);
297 complete(&dpaux->complete);
308 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
310 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
314 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
317 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
319 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
323 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
326 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
349 tegra_dpaux_pad_power_down(dpaux);
356 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
357 tegra_dpaux_pad_power_up(dpaux);
371 "dpaux-io",
434 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
436 return tegra_dpaux_pad_config(dpaux, function);
449 struct tegra_dpaux *dpaux;
454 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
455 if (!dpaux)
458 dpaux->soc = of_device_get_match_data(&pdev->dev);
459 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
460 init_completion(&dpaux->complete);
461 INIT_LIST_HEAD(&dpaux->list);
462 dpaux->dev = &pdev->dev;
465 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
466 if (IS_ERR(dpaux->regs))
467 return PTR_ERR(dpaux->regs);
469 dpaux->irq = platform_get_irq(pdev, 0);
470 if (dpaux->irq < 0)
471 return dpaux->irq;
474 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
475 if (IS_ERR(dpaux->rst)) {
478 PTR_ERR(dpaux->rst));
479 return PTR_ERR(dpaux->rst);
483 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
484 if (IS_ERR(dpaux->clk)) {
486 PTR_ERR(dpaux->clk));
487 return PTR_ERR(dpaux->clk);
490 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
491 if (IS_ERR(dpaux->clk_parent)) {
493 PTR_ERR(dpaux->clk_parent));
494 return PTR_ERR(dpaux->clk_parent);
497 err = clk_set_rate(dpaux->clk_parent, 270000000);
504 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
505 if (IS_ERR(dpaux->vdd)) {
506 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
507 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
510 PTR_ERR(dpaux->vdd));
512 return PTR_ERR(dpaux->vdd);
515 dpaux->vdd = NULL;
518 platform_set_drvdata(pdev, dpaux);
522 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
523 dev_name(dpaux->dev), dpaux);
525 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
526 dpaux->irq, err);
530 disable_irq(dpaux->irq);
532 dpaux->aux.transfer = tegra_dpaux_transfer;
533 dpaux->aux.dev = &pdev->dev;
535 err = drm_dp_aux_register(&dpaux->aux);
547 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
552 dpaux->desc.name = dev_name(&pdev->dev);
553 dpaux->desc.pins = tegra_dpaux_pins;
554 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
555 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
556 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
557 dpaux->desc.owner = THIS_MODULE;
559 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
560 if (IS_ERR(dpaux->pinctrl)) {
562 return PTR_ERR(dpaux->pinctrl);
568 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
569 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
572 list_add_tail(&dpaux->list, &dpaux_list);
580 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
582 cancel_work_sync(&dpaux->work);
585 tegra_dpaux_pad_power_down(dpaux);
590 drm_dp_aux_unregister(&dpaux->aux);
593 list_del(&dpaux->list);
602 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
605 if (dpaux->rst) {
606 err = reset_control_assert(dpaux->rst);
615 clk_disable_unprepare(dpaux->clk_parent);
616 clk_disable_unprepare(dpaux->clk);
623 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
626 err = clk_prepare_enable(dpaux->clk);
632 err = clk_prepare_enable(dpaux->clk_parent);
640 if (dpaux->rst) {
641 err = reset_control_deassert(dpaux->rst);
653 clk_disable_unprepare(dpaux->clk_parent);
655 clk_disable_unprepare(dpaux->clk);
683 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
684 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
685 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
686 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
693 .name = "tegra-dpaux",
703 struct tegra_dpaux *dpaux;
707 list_for_each_entry(dpaux, &dpaux_list, list)
708 if (np == dpaux->dev->of_node) {
710 return &dpaux->aux;
720 struct tegra_dpaux *dpaux = to_dpaux(aux);
725 dpaux->output = output;
730 if (dpaux->vdd) {
731 err = regulator_enable(dpaux->vdd);
751 enable_irq(dpaux->irq);
757 struct tegra_dpaux *dpaux = to_dpaux(aux);
761 disable_irq(dpaux->irq);
763 if (dpaux->output->panel) {
766 if (dpaux->vdd) {
767 err = regulator_disable(dpaux->vdd);
786 dpaux->output = NULL;
794 struct tegra_dpaux *dpaux = to_dpaux(aux);
797 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
807 struct tegra_dpaux *dpaux = to_dpaux(aux);
809 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
814 struct tegra_dpaux *dpaux = to_dpaux(aux);
816 tegra_dpaux_pad_power_down(dpaux);