Lines Matching refs:value
45 u32 value;
48 value = tegra_dc_readl(dc, offset);
51 return value;
83 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
186 * alpha blending, then bottom window is getting alpha value
290 u32 value;
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
345 u32 value;
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
377 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
378 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
390 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
391 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
407 value = window->stride[1] << 16 | window->stride[0];
408 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
417 unsigned long height = window->tiling.value;
421 value = DC_WINBUF_SURFACE_KIND_PITCH;
425 value = DC_WINBUF_SURFACE_KIND_TILED;
429 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
434 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
438 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
443 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
455 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
458 value = WIN_ENABLE;
471 value |= CSC_ENABLE;
473 value |= COLOR_EXPAND;
477 value |= H_DIRECTION;
480 value |= V_DIRECTION;
504 value |= H_FILTER;
517 value |= V_FILTER;
520 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
695 u32 value;
701 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
702 value &= ~WIN_ENABLE;
703 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
868 u32 value = CURSOR_CLIP_DISPLAY;
876 value |= CURSOR_SIZE_32x32;
880 value |= CURSOR_SIZE_64x64;
884 value |= CURSOR_SIZE_128x128;
888 value |= CURSOR_SIZE_256x256;
897 value |= (state->iova[0] >> 10) & 0x3fffff;
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
901 value = (state->iova[0] >> 32) & 0x3;
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
907 value |= CURSOR_ENABLE;
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
910 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
911 value &= ~CURSOR_DST_BLEND_MASK;
912 value &= ~CURSOR_SRC_BLEND_MASK;
913 value |= CURSOR_MODE_NORMAL;
914 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
915 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
916 value |= CURSOR_ALPHA;
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
920 value = (plane->state->crtc_y & 0x3fff) << 16 |
922 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
929 u32 value;
937 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
938 value &= ~CURSOR_ENABLE;
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1482 u32 value;
1491 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1492 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1498 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1499 seq_printf(s, "%08x\n", value);
1579 u32 value;
1581 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1582 value |= VBLANK_INT;
1583 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1591 u32 value;
1593 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1594 value &= ~VBLANK_INT;
1595 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1617 unsigned long value;
1622 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1623 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1626 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1628 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1630 value = ((mode->vtotal - mode->vsync_end) << 16) |
1632 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1634 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1636 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1638 value = (mode->vdisplay << 16) | mode->hdisplay;
1639 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1676 u32 value;
1709 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1710 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1716 u32 value;
1719 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1720 value &= ~DISP_CTRL_MODE_MASK;
1721 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1728 u32 value;
1730 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1732 return (value & DISP_CTRL_MODE_MASK) == 0;
1754 u32 value;
1761 * Ignore the return value, there isn't anything useful to do
1784 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1785 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1787 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1813 u32 value;
1831 value = SYNCPT_CNTRL_NO_STALL;
1832 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1834 value = enable | syncpt;
1835 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1839 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1841 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1843 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1848 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1850 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1852 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1854 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1855 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1859 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1861 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1863 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1865 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1868 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1870 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1872 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1874 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1876 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1878 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1880 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1882 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1898 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1899 value &= ~INTERLACE_ENABLE;
1900 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1903 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1904 value &= ~DISP_CTRL_MODE_MASK;
1905 value |= DISP_CTRL_MODE_C_DISPLAY;
1906 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1909 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1910 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1912 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1917 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1918 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1950 u32 value;
1952 value = state->planes << 8 | GENERAL_UPDATE;
1953 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1954 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1956 value = state->planes | GENERAL_ACT_REQ;
1957 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1958 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2458 u32 value = 0;
2461 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2483 value++;
2487 dc->pipe = value;