Lines Matching refs:tcon
83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
90 WARN_ON(!tcon->quirks->has_channel_0);
91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
94 clk = tcon->dclk;
97 WARN_ON(!tcon->quirks->has_channel_1);
98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
101 clk = tcon->sclk1;
117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
141 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
180 if (tcon->quirks->setup_lvds_phy)
181 tcon->quirks->setup_lvds_phy(tcon, encoder);
183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
188 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
213 sun4i_tcon_lvds_set_status(tcon, encoder, false);
215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
220 sun4i_tcon_lvds_set_status(tcon, encoder, true);
222 sun4i_tcon_channel_set_status(tcon, channel, enabled);
225 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
251 struct sun4i_tcon *tcon;
253 list_for_each_entry(tcon, &drv->tcon_list, list)
254 if (tcon->id == 0)
255 return tcon;
263 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
268 if (tcon->quirks->set_mux)
269 ret = tcon->quirks->set_mux(tcon, encoder);
293 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
305 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
372 sun4i_tcon0_mode_set_common(tcon, mode);
375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
428 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
436 WARN_ON(!tcon->quirks->has_channel_0);
438 tcon->dclk_min_div = 7;
439 tcon->dclk_max_div = 7;
440 sun4i_tcon0_mode_set_common(tcon, mode);
443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
483 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
492 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
495 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
500 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
503 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
513 WARN_ON(!tcon->quirks->has_channel_0);
515 tcon->dclk_min_div = tcon->quirks->dclk_min_div;
516 tcon->dclk_max_div = 127;
517 sun4i_tcon0_mode_set_common(tcon, mode);
520 sun4i_tcon0_mode_set_dithering(tcon, connector);
524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
575 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
583 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
588 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
591 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
598 WARN_ON(!tcon->quirks->has_channel_1);
601 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
605 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
614 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
619 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
624 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
629 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
637 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
663 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
671 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
676 if (tcon->quirks->polarity_in_ch0) {
685 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
696 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
700 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
705 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
712 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
715 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
718 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
719 sun4i_tcon_set_mux(tcon, 0, encoder);
723 sun4i_tcon1_mode_set(tcon, mode);
724 sun4i_tcon_set_mux(tcon, 1, encoder);
748 struct sun4i_tcon *tcon = private;
749 struct drm_device *drm = tcon->drm;
750 struct sun4i_crtc *scrtc = tcon->crtc;
754 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
765 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
778 struct sun4i_tcon *tcon)
780 tcon->clk = devm_clk_get_enabled(dev, "ahb");
781 if (IS_ERR(tcon->clk)) {
783 return PTR_ERR(tcon->clk);
786 if (tcon->quirks->has_channel_0) {
787 tcon->sclk0 = devm_clk_get_enabled(dev, "tcon-ch0");
788 if (IS_ERR(tcon->sclk0)) {
790 return PTR_ERR(tcon->sclk0);
794 if (tcon->quirks->has_channel_1) {
795 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
796 if (IS_ERR(tcon->sclk1)) {
798 return PTR_ERR(tcon->sclk1);
806 struct sun4i_tcon *tcon)
816 dev_name(dev), tcon);
833 struct sun4i_tcon *tcon)
844 tcon->regs = devm_regmap_init_mmio(dev, regs,
846 if (IS_ERR(tcon->regs)) {
848 return PTR_ERR(tcon->regs);
852 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
853 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
854 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
857 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
858 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
866 * the of_graph upwards to find the backend our tcon is connected to,
1111 struct sun4i_tcon *tcon;
1122 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
1123 if (!tcon)
1125 dev_set_drvdata(dev, tcon);
1126 tcon->drm = drm;
1127 tcon->dev = dev;
1128 tcon->id = engine->id;
1129 tcon->quirks = of_device_get_match_data(dev);
1131 tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
1132 if (IS_ERR(tcon->lcd_rst)) {
1134 return PTR_ERR(tcon->lcd_rst);
1137 if (tcon->quirks->needs_edp_reset) {
1152 ret = reset_control_reset(tcon->lcd_rst);
1158 if (tcon->quirks->supports_lvds) {
1166 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
1167 if (IS_ERR(tcon->lvds_rst)) {
1169 return PTR_ERR(tcon->lvds_rst);
1170 } else if (tcon->lvds_rst) {
1172 reset_control_reset(tcon->lvds_rst);
1184 if (tcon->quirks->has_lvds_alt) {
1185 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
1186 if (IS_ERR(tcon->lvds_pll)) {
1187 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
1191 return PTR_ERR(tcon->lvds_pll);
1199 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
1210 ret = sun4i_tcon_init_clocks(dev, tcon);
1216 ret = sun4i_tcon_init_regmap(dev, tcon);
1222 if (tcon->quirks->has_channel_0) {
1223 ret = sun4i_dclk_create(dev, tcon);
1230 ret = sun4i_tcon_init_irq(dev, tcon);
1236 tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
1237 if (IS_ERR(tcon->crtc)) {
1239 ret = PTR_ERR(tcon->crtc);
1243 if (tcon->quirks->has_channel_0) {
1252 ret = sun4i_lvds_init(drm, tcon);
1256 ret = sun4i_rgb_init(drm, tcon);
1263 if (tcon->quirks->needs_de_be_mux) {
1274 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
1276 tcon->id);
1277 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
1279 tcon->id);
1282 list_add_tail(&tcon->list, &drv->tcon_list);
1287 if (tcon->quirks->has_channel_0)
1288 sun4i_dclk_free(tcon);
1290 reset_control_assert(tcon->lcd_rst);
1297 struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1299 list_del(&tcon->list);
1300 if (tcon->quirks->has_channel_0)
1301 sun4i_dclk_free(tcon);
1337 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1356 0x3 << shift, tcon->id << shift);
1361 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1374 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1377 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1397 0x3 << shift, tcon->id << shift);
1402 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
1411 port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
1418 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
1437 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
1538 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1539 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1540 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1541 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1542 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1545 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1546 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1547 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1548 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1549 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1550 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1551 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1552 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1562 .name = "sun4i-tcon",