Lines Matching defs:backend
34 /* backend <-> TCON muxing selection done in backend */
80 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
93 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
168 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
178 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
186 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
193 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
200 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
211 regmap_write(backend->engine.regs,
219 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
252 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
257 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
267 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
274 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
278 DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
284 regmap_update_bits(backend->engine.regs,
291 return sun4i_backend_update_yuv_format(backend, layer, plane);
299 regmap_update_bits(backend->engine.regs,
306 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
318 regmap_update_bits(backend->engine.regs,
323 regmap_update_bits(backend->engine.regs,
330 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
336 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
339 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
345 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
355 regmap_write(backend->engine.regs,
364 return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
369 regmap_write(backend->engine.regs,
376 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
383 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
393 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
402 void sun4i_backend_cleanup_layer(struct sun4i_backend *backend,
405 regmap_update_bits(backend->engine.regs,
428 struct sun4i_backend *backend = layer->backend;
432 if (IS_ERR(backend->frontend))
442 * TODO: The backend alone allows 2x and 4x integer scaling, including
444 * Use the backend directly instead of the frontend in this case, with
452 * Here the format is supported by both the frontend and the backend
453 * and no frontend scaling is required, so use the backend directly.
490 struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
583 if (backend->quirks->supports_lowest_plane_alpha)
592 if (!backend->quirks->supports_lowest_plane_alpha &&
631 struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
632 struct sun4i_frontend *frontend = backend->frontend;
642 * This is due to the fact that the backend will not take into
651 spin_lock(&backend->frontend_lock);
652 if (backend->frontend_teardown) {
654 backend->frontend_teardown = false;
656 spin_unlock(&backend->frontend_lock);
660 struct sun4i_backend *backend = dev_get_drvdata(dev);
663 backend->sat_reset = devm_reset_control_get(dev, "sat");
664 if (IS_ERR(backend->sat_reset)) {
666 return PTR_ERR(backend->sat_reset);
669 ret = reset_control_deassert(backend->sat_reset);
675 backend->sat_clk = devm_clk_get(dev, "sat");
676 if (IS_ERR(backend->sat_clk)) {
678 ret = PTR_ERR(backend->sat_clk);
682 ret = clk_prepare_enable(backend->sat_clk);
691 reset_control_assert(backend->sat_reset);
696 struct sun4i_backend *backend = dev_get_drvdata(dev);
698 clk_disable_unprepare(backend->sat_clk);
699 reset_control_assert(backend->sat_reset);
705 * The display backend can take video output from the display frontend, or
708 * tree with of_graph, and we use it here to figure out which backend, if
785 struct sun4i_backend *backend;
791 backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
792 if (!backend)
794 dev_set_drvdata(dev, backend);
795 spin_lock_init(&backend->frontend_lock);
829 backend->engine.node = dev->of_node;
830 backend->engine.ops = &sun4i_backend_engine_ops;
831 backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
832 if (backend->engine.id < 0)
833 return backend->engine.id;
835 backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
836 if (IS_ERR(backend->frontend))
844 backend->reset = devm_reset_control_get(dev, NULL);
845 if (IS_ERR(backend->reset)) {
847 return PTR_ERR(backend->reset);
850 ret = reset_control_deassert(backend->reset);
856 backend->bus_clk = devm_clk_get(dev, "ahb");
857 if (IS_ERR(backend->bus_clk)) {
858 dev_err(dev, "Couldn't get the backend bus clock\n");
859 ret = PTR_ERR(backend->bus_clk);
862 clk_prepare_enable(backend->bus_clk);
864 backend->mod_clk = devm_clk_get(dev, "mod");
865 if (IS_ERR(backend->mod_clk)) {
866 dev_err(dev, "Couldn't get the backend module clock\n");
867 ret = PTR_ERR(backend->mod_clk);
871 ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
877 clk_prepare_enable(backend->mod_clk);
879 backend->ram_clk = devm_clk_get(dev, "ram");
880 if (IS_ERR(backend->ram_clk)) {
881 dev_err(dev, "Couldn't get the backend RAM clock\n");
882 ret = PTR_ERR(backend->ram_clk);
885 clk_prepare_enable(backend->ram_clk);
888 "allwinner,sun8i-a33-display-backend")) {
896 backend->engine.regs = devm_regmap_init_mmio(dev, regs,
898 if (IS_ERR(backend->engine.regs)) {
899 dev_err(dev, "Couldn't create the backend regmap\n");
900 return PTR_ERR(backend->engine.regs);
903 list_add_tail(&backend->engine.list, &drv->engine_list);
906 * Many of the backend's layer configuration registers have
914 regmap_write(backend->engine.regs, i, 0);
917 regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
920 /* Enable the backend */
921 regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
930 * and TCONs, so we select the backend with same ID.
938 regmap_update_bits(backend->engine.regs,
941 (backend->engine.id
946 backend->quirks = quirks;
951 clk_disable_unprepare(backend->ram_clk);
953 clk_rate_exclusive_put(backend->mod_clk);
954 clk_disable_unprepare(backend->mod_clk);
956 clk_disable_unprepare(backend->bus_clk);
958 reset_control_assert(backend->reset);
965 struct sun4i_backend *backend = dev_get_drvdata(dev);
967 list_del(&backend->engine.list);
970 "allwinner,sun8i-a33-display-backend"))
973 clk_disable_unprepare(backend->ram_clk);
974 clk_rate_exclusive_put(backend->mod_clk);
975 clk_disable_unprepare(backend->mod_clk);
976 clk_disable_unprepare(backend->bus_clk);
977 reset_control_assert(backend->reset);
1020 .compatible = "allwinner,sun4i-a10-display-backend",
1024 .compatible = "allwinner,sun5i-a13-display-backend",
1028 .compatible = "allwinner,sun6i-a31-display-backend",
1032 .compatible = "allwinner,sun7i-a20-display-backend",
1036 .compatible = "allwinner,sun8i-a23-display-backend",
1040 .compatible = "allwinner,sun8i-a33-display-backend",
1044 .compatible = "allwinner,sun9i-a80-display-backend",
1055 .name = "sun4i-backend",