Lines Matching defs:ldev
55 #define REG_OFS (ldev->caps.reg_ofs)
369 struct ltdc_device *ldev = ddev->dev_private;
373 if (ldev->irq_status & ISR_LIF)
377 mutex_lock(&ldev->err_lock);
378 if (ldev->irq_status & ISR_FUIF)
379 ldev->error_status |= ISR_FUIF;
380 if (ldev->irq_status & ISR_TERRIF)
381 ldev->error_status |= ISR_TERRIF;
382 mutex_unlock(&ldev->err_lock);
390 struct ltdc_device *ldev = ddev->dev_private;
393 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
394 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
405 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
418 reg_write(ldev->regs, LTDC_L1CLUTWR, val);
425 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
433 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
436 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
439 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
447 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
455 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
458 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
469 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
475 result = clk_round_rate(ldev->pixel_clk, target);
480 if (result > ldev->caps.pad_max_freq_hz)
508 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
511 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
516 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
526 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
609 reg_update_bits(ldev->regs, LTDC_GCR,
614 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
618 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
622 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
626 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
628 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
634 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
643 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
664 struct ltdc_device *ldev = ddev->dev_private;
685 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
686 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
687 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
688 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
718 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
724 reg_set(ldev->regs, LTDC_IER, IER_LIE);
733 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
736 reg_clear(ldev->regs, LTDC_IER, IER_LIE);
783 struct ltdc_device *ldev = plane_to_ltdc(plane);
812 bpcr = reg_read(ldev->regs, LTDC_BPCR);
818 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
823 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
829 if (ldev->caps.pix_fmt_hw[val] == pf)
837 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
842 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
844 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
849 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
857 if (ldev->caps.non_alpha_only_l1 &&
861 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
866 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
872 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
877 reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
880 ldev->plane_fpsi[plane->index].counter++;
882 mutex_lock(&ldev->err_lock);
883 if (ldev->error_status & ISR_FUIF) {
885 ldev->error_status &= ~ISR_FUIF;
887 if (ldev->error_status & ISR_TERRIF) {
889 ldev->error_status &= ~ISR_TERRIF;
891 mutex_unlock(&ldev->err_lock);
897 struct ltdc_device *ldev = plane_to_ltdc(plane);
901 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
911 struct ltdc_device *ldev = plane_to_ltdc(plane);
912 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
958 struct ltdc_device *ldev = ddev->dev_private;
969 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
980 if (ldev->caps.non_alpha_only_l1 &&
1015 struct ltdc_device *ldev = ddev->dev_private;
1041 for (i = 1; i < ldev->caps.nb_layers; i++) {
1068 struct ltdc_device *ldev = ddev->dev_private;
1073 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
1082 struct ltdc_device *ldev = ddev->dev_private;
1087 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
1143 struct ltdc_device *ldev = ddev->dev_private;
1150 lcr = reg_read(ldev->regs, LTDC_LCR);
1152 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1155 gc2r = reg_read(ldev->regs, LTDC_GC2R);
1157 ldev->caps.bus_width = 8 << bus_width_log2;
1158 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
1160 switch (ldev->caps.hw_version) {
1163 ldev->caps.reg_ofs = REG_OFS_NONE;
1164 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1172 ldev->caps.non_alpha_only_l1 = true;
1173 ldev->caps.pad_max_freq_hz = 90000000;
1174 if (ldev->caps.hw_version == HWVER_10200)
1175 ldev->caps.pad_max_freq_hz = 65000000;
1176 ldev->caps.nb_irq = 2;
1179 ldev->caps.reg_ofs = REG_OFS_4;
1180 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1181 ldev->caps.non_alpha_only_l1 = false;
1182 ldev->caps.pad_max_freq_hz = 150000000;
1183 ldev->caps.nb_irq = 4;
1194 struct ltdc_device *ldev = ddev->dev_private;
1197 clk_disable_unprepare(ldev->pixel_clk);
1202 struct ltdc_device *ldev = ddev->dev_private;
1207 ret = clk_prepare_enable(ldev->pixel_clk);
1219 struct ltdc_device *ldev = ddev->dev_private;
1237 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1238 if (IS_ERR(ldev->pixel_clk)) {
1239 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1241 return PTR_ERR(ldev->pixel_clk);
1244 if (clk_prepare_enable(ldev->pixel_clk)) {
1284 mutex_init(&ldev->err_lock);
1293 ldev->regs = devm_ioremap_resource(dev, res);
1294 if (IS_ERR(ldev->regs)) {
1296 ret = PTR_ERR(ldev->regs);
1301 reg_clear(ldev->regs, LTDC_IER,
1307 ldev->caps.hw_version);
1311 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1313 for (i = 0; i < ldev->caps.nb_irq; i++) {
1354 clk_disable_unprepare(ldev->pixel_clk);
1365 clk_disable_unprepare(ldev->pixel_clk);