Lines Matching refs:ret
371 int ret, i, vco;
398 ret = clk_prepare_enable(dsi->phy_cfg_clk);
399 if (ret) {
401 return ret;
481 return ret;
487 int ret;
489 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
490 if (ret) {
491 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
749 int ret, mux;
765 ret = clk_prepare_enable(dsi->grf_clk);
766 if (ret) {
767 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
798 int ret;
803 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
804 if (ret) {
806 return ret;
882 int ret;
921 ret = clk_prepare_enable(dsi->pllref_clk);
922 if (ret) {
923 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
924 return ret;
933 ret = clk_prepare_enable(dsi->grf_clk);
934 if (ret) {
935 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
936 return ret;
945 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
946 if (ret) {
948 return ret;
951 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
952 if (ret) {
953 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
954 return ret;
984 int ret;
986 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
987 if (ret) {
989 ret);
990 return ret;
997 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
998 if (ret) {
1001 ret);
1002 return ret;
1037 int ret, i;
1068 ret = PTR_ERR(dsi->phy);
1069 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1070 return ret;
1082 ret = PTR_ERR(dsi->pllref_clk);
1085 ret);
1086 return ret;
1093 ret = PTR_ERR(dsi->phy_cfg_clk);
1095 "Unable to get phy_cfg_clk: %d\n", ret);
1096 return ret;
1103 ret = PTR_ERR(dsi->grf_clk);
1104 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1105 return ret;
1125 ret = PTR_ERR(dsi->dmd);
1126 if (ret != -EPROBE_DEFER)
1128 "Failed to probe dw_mipi_dsi: %d\n", ret);
1136 return ret;