Lines Matching refs:dsi
309 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
311 writel(val, dsi->base + reg);
314 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
316 return readl(dsi->base + reg);
319 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
321 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
324 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
327 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
330 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
339 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
341 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
344 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
346 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
349 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
355 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
357 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
363 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
365 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
370 struct dw_mipi_dsi_rockchip *dsi = priv_data;
373 if (dsi->phy)
388 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
390 i = max_mbps_to_parameter(dsi->lane_mbps);
392 DRM_DEV_ERROR(dsi->dev,
394 dsi->lane_mbps);
398 ret = clk_prepare_enable(dsi->phy_cfg_clk);
400 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
404 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
410 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
412 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
416 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
419 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
420 INPUT_DIVIDER(dsi->input_div));
421 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
422 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
430 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
432 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
433 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
435 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
438 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
440 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
443 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
447 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
450 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
455 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
456 TLP_PROGRAM_EN | ns2bc(dsi, 500));
457 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
458 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
459 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
460 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
461 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
462 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
463 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
464 BIT(5) | ns2bc(dsi, 100));
465 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
466 BIT(5) | (ns2bc(dsi, 60) + 7));
468 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
469 TLP_PROGRAM_EN | ns2bc(dsi, 500));
470 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
471 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
472 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
473 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
474 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
475 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
476 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
477 BIT(5) | ns2bc(dsi, 100));
479 clk_disable_unprepare(dsi->phy_cfg_clk);
486 struct dw_mipi_dsi_rockchip *dsi = priv_data;
489 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
491 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
495 phy_configure(dsi->phy, &dsi->phy_opts);
496 phy_power_on(dsi->phy);
501 struct dw_mipi_dsi_rockchip *dsi = priv_data;
503 phy_power_off(dsi->phy);
511 struct dw_mipi_dsi_rockchip *dsi = priv_data;
523 dsi->format = format;
524 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
526 DRM_DEV_ERROR(dsi->dev,
528 dsi->format);
539 DRM_DEV_ERROR(dsi->dev,
544 if (dsi->phy) {
547 &dsi->phy_opts.mipi_dphy);
548 dsi->lane_mbps = target_mbps;
549 *lane_mbps = dsi->lane_mbps;
554 fin = clk_get_rate(dsi->pllref_clk);
597 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
598 *lane_mbps = dsi->lane_mbps;
599 dsi->input_div = best_prediv;
600 dsi->feedback_div = best_fbdiv;
602 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
694 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
696 if (dsi->cdata->lanecfg1_grf_reg)
697 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
698 dsi->cdata->lanecfg1);
700 if (dsi->cdata->lanecfg2_grf_reg)
701 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
702 dsi->cdata->lanecfg2);
704 if (dsi->cdata->enable_grf_reg)
705 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
706 dsi->cdata->enable);
709 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
712 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
713 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
722 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
724 switch (dsi->format) {
740 if (dsi->slave)
748 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
751 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
752 &dsi->encoder);
756 pm_runtime_get_sync(dsi->dev);
757 if (dsi->slave)
758 pm_runtime_get_sync(dsi->slave->dev);
765 ret = clk_prepare_enable(dsi->grf_clk);
767 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
771 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
772 if (dsi->slave)
773 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
775 clk_disable_unprepare(dsi->grf_clk);
780 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
782 if (dsi->slave)
783 pm_runtime_put(dsi->slave->dev);
784 pm_runtime_put(dsi->dev);
794 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
797 struct drm_encoder *encoder = &dsi->encoder;
801 dsi->dev->of_node);
815 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
820 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
822 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
831 if (node == dsi->dev->of_node)
878 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
884 second = dw_mipi_dsi_rockchip_find_second(dsi);
889 master1 = of_property_read_bool(dsi->dev->of_node,
895 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
900 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
906 dsi->is_slave = true;
910 dsi->slave = dev_get_drvdata(second);
911 if (!dsi->slave) {
916 dsi->slave->is_slave = true;
917 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
921 ret = clk_prepare_enable(dsi->pllref_clk);
933 ret = clk_prepare_enable(dsi->grf_clk);
935 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
939 dw_mipi_dsi_rockchip_config(dsi);
940 if (dsi->slave)
941 dw_mipi_dsi_rockchip_config(dsi->slave);
943 clk_disable_unprepare(dsi->grf_clk);
945 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
951 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
964 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
966 if (dsi->is_slave)
969 dw_mipi_dsi_unbind(dsi->dmd);
971 clk_disable_unprepare(dsi->pllref_clk);
982 struct dw_mipi_dsi_rockchip *dsi = priv_data;
986 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
988 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
993 second = dw_mipi_dsi_rockchip_find_second(dsi);
1012 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1015 second = dw_mipi_dsi_rockchip_find_second(dsi);
1019 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1033 struct dw_mipi_dsi_rockchip *dsi;
1039 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1040 if (!dsi)
1044 dsi->base = devm_ioremap_resource(dev, res);
1045 if (IS_ERR(dsi->base)) {
1046 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1047 return PTR_ERR(dsi->base);
1053 dsi->cdata = &cdata[i];
1060 if (!dsi->cdata) {
1061 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1066 dsi->phy = devm_phy_optional_get(dev, "dphy");
1067 if (IS_ERR(dsi->phy)) {
1068 ret = PTR_ERR(dsi->phy);
1073 dsi->pllref_clk = devm_clk_get(dev, "ref");
1074 if (IS_ERR(dsi->pllref_clk)) {
1075 if (dsi->phy) {
1080 dsi->pllref_clk = NULL;
1082 ret = PTR_ERR(dsi->pllref_clk);
1090 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1091 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1092 if (IS_ERR(dsi->phy_cfg_clk)) {
1093 ret = PTR_ERR(dsi->phy_cfg_clk);
1100 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1101 dsi->grf_clk = devm_clk_get(dev, "grf");
1102 if (IS_ERR(dsi->grf_clk)) {
1103 ret = PTR_ERR(dsi->grf_clk);
1109 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1110 if (IS_ERR(dsi->grf_regmap)) {
1111 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
1112 return PTR_ERR(dsi->grf_regmap);
1115 dsi->dev = dev;
1116 dsi->pdata.base = dsi->base;
1117 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1118 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1119 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1120 dsi->pdata.priv_data = dsi;
1121 platform_set_drvdata(pdev, dsi);
1123 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1124 if (IS_ERR(dsi->dmd)) {
1125 ret = PTR_ERR(dsi->dmd);
1135 clk_disable_unprepare(dsi->pllref_clk);
1141 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1143 dw_mipi_dsi_remove(dsi->dmd);
1234 .compatible = "rockchip,px30-mipi-dsi",
1237 .compatible = "rockchip,rk3288-mipi-dsi",
1240 .compatible = "rockchip,rk3399-mipi-dsi",
1252 .name = "dw-mipi-dsi-rockchip",