Lines Matching refs:value
366 u32 value;
378 value = RREG32_SMC(GFX_POWER_GATING_CNTL);
379 value &= ~(SSSD_MASK | PDS_DIV_MASK);
381 value |= SSSD(1);
382 value |= PDS_DIV(dividers.post_div);
383 WREG32_SMC(GFX_POWER_GATING_CNTL, value);
519 u32 value;
522 value = RREG32_SMC(PM_I_CNTL_1);
523 value &= ~DS_PG_CNTL_MASK;
524 value |= DS_PG_CNTL(1);
525 WREG32_SMC(PM_I_CNTL_1, value);
527 value = RREG32_SMC(SMU_S_PG_CNTL);
528 value &= ~DS_PG_EN_MASK;
529 value |= DS_PG_EN(1);
530 WREG32_SMC(SMU_S_PG_CNTL, value);
532 value = RREG32_SMC(SMU_S_PG_CNTL);
533 value &= ~DS_PG_EN_MASK;
534 WREG32_SMC(SMU_S_PG_CNTL, value);
536 value = RREG32_SMC(PM_I_CNTL_1);
537 value &= ~DS_PG_CNTL_MASK;
538 WREG32_SMC(PM_I_CNTL_1, value);
588 u32 value;
596 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
597 value &= ~CLK_DIVIDER_MASK;
598 value |= CLK_DIVIDER(dividers.post_div);
599 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
606 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
607 value &= ~PD_SCLK_DIVIDER_MASK;
608 value |= PD_SCLK_DIVIDER(dividers.post_div);
609 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
615 u32 value;
618 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
619 value &= ~DS_DIV_MASK;
620 value |= DS_DIV(divider);
621 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
627 u32 value;
630 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
631 value &= ~DS_SH_DIV_MASK;
632 value |= DS_SH_DIV(divider);
633 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
640 u32 value;
643 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
644 value &= ~VID_MASK;
645 value |= VID(vid_7bit);
646 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
648 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
649 value &= ~LVRT_MASK;
650 value |= LVRT(0);
651 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
657 u32 value;
660 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
661 value &= ~GNB_SLOW_MASK;
662 value |= GNB_SLOW(gnb_slow);
663 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
669 u32 value;
672 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
673 value &= ~FORCE_NBPS1_MASK;
674 value |= FORCE_NBPS1(force_nbp_state);
675 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
681 u32 value;
684 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
685 value &= ~DISPLAY_WM_MASK;
686 value |= DISPLAY_WM(wm);
687 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
693 u32 value;
696 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
697 value &= ~VCE_WM_MASK;
698 value |= VCE_WM(wm);
699 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
705 u32 value;
708 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);
709 value &= ~AT_MASK;
710 value |= AT(at);
711 WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);
736 u32 value;
739 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
740 value &= ~STATE_VALID_MASK;
742 value |= STATE_VALID(1);
743 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
756 u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);
758 value &= ~(SCLK_DPM_EN_MASK | SCLK_DPM_BOOT_STATE_MASK | VOLTAGE_CHG_EN_MASK);
759 value |= SCLK_DPM_EN(1) | SCLK_DPM_BOOT_STATE(0) | VOLTAGE_CHG_EN(1);
760 WREG32_SMC(SMU_SCLK_DPM_CNTL, value);
1008 u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);
1010 value &= ~(HT_MASK | LT_MASK);
1011 value |= HT((pi->thermal_auto_throttling + 49) * 8);
1012 value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8);
1013 WREG32_SMC(SMU_SCLK_DPM_TTT, value);
1018 u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);
1020 value &= ~SCLK_TT_EN_MASK;
1021 value |= SCLK_TT_EN(1);
1022 WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value);
1031 u32 value;
1037 value = RREG32_SMC(PM_I_CNTL_1);
1038 value &= ~SCLK_DPM_MASK;
1039 value |= SCLK_DPM(ni);
1040 WREG32_SMC(PM_I_CNTL_1, value);