Lines Matching defs:rdev
81 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
83 struct sumo_power_info *pi = rdev->pm.dpm.priv;
88 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
103 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
120 static void sumo_program_git(struct radeon_device *rdev)
123 u32 xclk = radeon_get_xclk(rdev);
131 static void sumo_program_grsd(struct radeon_device *rdev)
134 u32 xclk = radeon_get_xclk(rdev);
142 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
144 sumo_program_git(rdev);
145 sumo_program_grsd(rdev);
148 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
154 u32 xclk = radeon_get_xclk(rdev);
156 if (rdev->family == CHIP_PALM) {
184 if (rdev->family == CHIP_PALM) {
196 if (rdev->family == CHIP_PALM) {
217 if (rdev->family == CHIP_PALM)
220 sumo_smu_pg_init(rdev);
226 if (rdev->family == CHIP_PALM) {
232 if (rdev->family == CHIP_PALM) {
244 sumo_smu_pg_init(rdev);
251 if (rdev->family == CHIP_PALM) {
259 if (rdev->family == CHIP_PALM) {
271 sumo_smu_pg_init(rdev);
274 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
284 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
286 struct sumo_power_info *pi = sumo_get_pi(rdev);
289 sumo_gfx_clockgating_initialize(rdev);
291 sumo_gfx_powergating_initialize(rdev);
293 sumo_mg_clockgating_enable(rdev, true);
295 sumo_gfx_clockgating_enable(rdev, true);
297 sumo_gfx_powergating_enable(rdev, true);
302 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
304 struct sumo_power_info *pi = sumo_get_pi(rdev);
307 sumo_gfx_clockgating_enable(rdev, false);
309 sumo_gfx_powergating_enable(rdev, false);
311 sumo_mg_clockgating_enable(rdev, false);
314 static void sumo_calculate_bsp(struct radeon_device *rdev,
317 struct sumo_power_info *pi = sumo_get_pi(rdev);
318 u32 xclk = radeon_get_xclk(rdev);
333 static void sumo_init_bsp(struct radeon_device *rdev)
335 struct sumo_power_info *pi = sumo_get_pi(rdev);
341 static void sumo_program_bsp(struct radeon_device *rdev,
344 struct sumo_power_info *pi = sumo_get_pi(rdev);
352 sumo_calculate_bsp(rdev, highest_engine_clock);
363 static void sumo_write_at(struct radeon_device *rdev,
384 static void sumo_program_at(struct radeon_device *rdev,
387 struct sumo_power_info *pi = sumo_get_pi(rdev);
415 sumo_write_at(rdev, i, a_t);
426 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
430 static void sumo_program_tp(struct radeon_device *rdev)
452 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
457 void sumo_clear_vc(struct radeon_device *rdev)
462 void sumo_program_sstp(struct radeon_device *rdev)
465 u32 xclk = radeon_get_xclk(rdev);
473 static void sumo_set_divider_value(struct radeon_device *rdev,
493 static void sumo_set_ds_dividers(struct radeon_device *rdev,
496 struct sumo_power_info *pi = sumo_get_pi(rdev);
507 static void sumo_set_ss_dividers(struct radeon_device *rdev,
510 struct sumo_power_info *pi = sumo_get_pi(rdev);
521 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
530 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
532 struct sumo_power_info *pi = sumo_get_pi(rdev);
546 static void sumo_program_power_level(struct radeon_device *rdev,
549 struct sumo_power_info *pi = sumo_get_pi(rdev);
554 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
559 sumo_set_divider_value(rdev, index, dividers.post_div);
561 sumo_set_vid(rdev, index, pl->vddc_index);
567 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
568 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
574 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
577 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
580 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
599 static bool sumo_dpm_enabled(struct radeon_device *rdev)
607 static void sumo_start_dpm(struct radeon_device *rdev)
612 static void sumo_stop_dpm(struct radeon_device *rdev)
617 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
625 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
629 sumo_set_forced_mode(rdev, true);
630 for (i = 0; i < rdev->usec_timeout; i++) {
637 static void sumo_wait_for_level_0(struct radeon_device *rdev)
641 for (i = 0; i < rdev->usec_timeout; i++) {
646 for (i = 0; i < rdev->usec_timeout; i++) {
653 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
655 sumo_set_forced_mode(rdev, false);
658 static void sumo_enable_power_level_0(struct radeon_device *rdev)
660 sumo_power_level_enable(rdev, 0, true);
663 static void sumo_patch_boost_state(struct radeon_device *rdev,
666 struct sumo_power_info *pi = sumo_get_pi(rdev);
677 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
692 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
695 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
710 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
713 static void sumo_enable_boost(struct radeon_device *rdev,
721 sumo_boost_state_enable(rdev, true);
723 sumo_boost_state_enable(rdev, false);
726 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
731 static void sumo_set_forced_level_0(struct radeon_device *rdev)
733 sumo_set_forced_level(rdev, 0);
736 static void sumo_program_wl(struct radeon_device *rdev,
751 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
755 struct sumo_power_info *pi = sumo_get_pi(rdev);
762 sumo_program_power_level(rdev, &new_ps->levels[i], i);
763 sumo_power_level_enable(rdev, i, true);
767 sumo_power_level_enable(rdev, i, false);
770 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
773 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
778 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
783 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
785 struct sumo_power_info *pi = sumo_get_pi(rdev);
789 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
799 static void sumo_program_bootup_state(struct radeon_device *rdev)
801 struct sumo_power_info *pi = sumo_get_pi(rdev);
805 sumo_program_power_level(rdev, &pi->boot_pl, 0);
811 sumo_power_level_enable(rdev, i, false);
814 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
818 struct sumo_power_info *pi = sumo_get_pi(rdev);
821 sumo_gfx_powergating_enable(rdev, false);
824 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
829 sumo_gfx_powergating_enable(rdev, true);
833 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
848 sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
851 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
866 sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
869 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
888 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
909 static void sumo_program_bootup_at(struct radeon_device *rdev)
915 static void sumo_reset_am(struct radeon_device *rdev)
920 static void sumo_start_am(struct radeon_device *rdev)
925 static void sumo_program_ttp(struct radeon_device *rdev)
927 u32 xclk = radeon_get_xclk(rdev);
940 static void sumo_program_ttt(struct radeon_device *rdev)
943 struct sumo_power_info *pi = sumo_get_pi(rdev);
952 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
963 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
969 static void sumo_program_dc_hto(struct radeon_device *rdev)
973 u32 xclk = radeon_get_xclk(rdev);
984 static void sumo_force_nbp_state(struct radeon_device *rdev,
987 struct sumo_power_info *pi = sumo_get_pi(rdev);
1003 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1007 struct sumo_power_info *pi = sumo_get_pi(rdev);
1028 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1031 struct sumo_power_info *pi = sumo_get_pi(rdev);
1042 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1046 struct sumo_power_info *pi = sumo_get_pi(rdev);
1066 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1069 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1086 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1092 struct sumo_power_info *pi = sumo_get_pi(rdev);
1099 return sumo_patch_thermal_state(rdev, ps, current_ps);
1117 sumo_get_valid_engine_clock(rdev, min_sclk);
1120 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1123 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1151 static void sumo_cleanup_asic(struct radeon_device *rdev)
1153 sumo_take_smu_control(rdev, false);
1156 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1174 rdev->pm.dpm.thermal.min_temp = low_temp;
1175 rdev->pm.dpm.thermal.max_temp = high_temp;
1180 static void sumo_update_current_ps(struct radeon_device *rdev,
1184 struct sumo_power_info *pi = sumo_get_pi(rdev);
1191 static void sumo_update_requested_ps(struct radeon_device *rdev,
1195 struct sumo_power_info *pi = sumo_get_pi(rdev);
1202 int sumo_dpm_enable(struct radeon_device *rdev)
1204 struct sumo_power_info *pi = sumo_get_pi(rdev);
1206 if (sumo_dpm_enabled(rdev))
1209 sumo_program_bootup_state(rdev);
1210 sumo_init_bsp(rdev);
1211 sumo_reset_am(rdev);
1212 sumo_program_tp(rdev);
1213 sumo_program_bootup_at(rdev);
1214 sumo_start_am(rdev);
1216 sumo_program_ttp(rdev);
1217 sumo_program_ttt(rdev);
1219 sumo_program_dc_hto(rdev);
1220 sumo_program_power_level_enter_state(rdev);
1221 sumo_enable_voltage_scaling(rdev, true);
1222 sumo_program_sstp(rdev);
1223 sumo_program_vc(rdev, SUMO_VRC_DFLT);
1224 sumo_override_cnb_thermal_events(rdev);
1225 sumo_start_dpm(rdev);
1226 sumo_wait_for_level_0(rdev);
1228 sumo_enable_sclk_ds(rdev, true);
1230 sumo_enable_boost_timer(rdev);
1232 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1237 int sumo_dpm_late_enable(struct radeon_device *rdev)
1241 ret = sumo_enable_clock_power_gating(rdev);
1245 if (rdev->irq.installed &&
1246 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1247 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1250 rdev->irq.dpm_thermal = true;
1251 radeon_irq_set(rdev);
1257 void sumo_dpm_disable(struct radeon_device *rdev)
1259 struct sumo_power_info *pi = sumo_get_pi(rdev);
1261 if (!sumo_dpm_enabled(rdev))
1263 sumo_disable_clock_power_gating(rdev);
1265 sumo_enable_sclk_ds(rdev, false);
1266 sumo_clear_vc(rdev);
1267 sumo_wait_for_level_0(rdev);
1268 sumo_stop_dpm(rdev);
1269 sumo_enable_voltage_scaling(rdev, false);
1271 if (rdev->irq.installed &&
1272 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1273 rdev->irq.dpm_thermal = false;
1274 radeon_irq_set(rdev);
1277 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1280 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1282 struct sumo_power_info *pi = sumo_get_pi(rdev);
1283 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1286 sumo_update_requested_ps(rdev, new_ps);
1289 sumo_apply_state_adjust_rules(rdev,
1296 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1298 struct sumo_power_info *pi = sumo_get_pi(rdev);
1303 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1305 sumo_enable_boost(rdev, new_ps, false);
1306 sumo_patch_boost_state(rdev, new_ps);
1309 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1310 sumo_enable_power_level_0(rdev);
1311 sumo_set_forced_level_0(rdev);
1312 sumo_set_forced_mode_enabled(rdev);
1313 sumo_wait_for_level_0(rdev);
1314 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1315 sumo_program_wl(rdev, new_ps);
1316 sumo_program_bsp(rdev, new_ps);
1317 sumo_program_at(rdev, new_ps);
1318 sumo_force_nbp_state(rdev, new_ps);
1319 sumo_set_forced_mode_disabled(rdev);
1320 sumo_set_forced_mode_enabled(rdev);
1321 sumo_set_forced_mode_disabled(rdev);
1322 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1325 sumo_enable_boost(rdev, new_ps, true);
1327 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1332 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1334 struct sumo_power_info *pi = sumo_get_pi(rdev);
1337 sumo_update_current_ps(rdev, new_ps);
1341 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1343 sumo_program_bootup_state(rdev);
1344 sumo_enable_power_level_0(rdev);
1345 sumo_set_forced_level_0(rdev);
1346 sumo_set_forced_mode_enabled(rdev);
1347 sumo_wait_for_level_0(rdev);
1348 sumo_set_forced_mode_disabled(rdev);
1349 sumo_set_forced_mode_enabled(rdev);
1350 sumo_set_forced_mode_disabled(rdev);
1354 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1356 struct sumo_power_info *pi = sumo_get_pi(rdev);
1358 sumo_initialize_m3_arb(rdev);
1359 pi->fw_version = sumo_get_running_fw_version(rdev);
1361 sumo_program_acpi_power_level(rdev);
1362 sumo_enable_acpi_pm(rdev);
1363 sumo_take_smu_control(rdev, true);
1366 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1392 static void sumo_patch_boot_state(struct radeon_device *rdev,
1395 struct sumo_power_info *pi = sumo_get_pi(rdev);
1402 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1422 rdev->pm.dpm.boot_ps = rps;
1423 sumo_patch_boot_state(rdev, ps);
1426 rdev->pm.dpm.uvd_ps = rps;
1429 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1433 struct sumo_power_info *pi = sumo_get_pi(rdev);
1452 static int sumo_parse_power_table(struct radeon_device *rdev)
1454 struct radeon_mode_info *mode_info = &rdev->mode_info;
1484 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
1487 if (!rdev->pm.dpm.ps)
1496 if (!rdev->pm.power_state[i].clock_info) {
1497 kfree(rdev->pm.dpm.ps);
1502 kfree(rdev->pm.dpm.ps);
1505 rdev->pm.dpm.ps[i].ps_priv = ps;
1516 sumo_parse_pplib_clock_info(rdev,
1517 &rdev->pm.dpm.ps[i], k,
1521 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1526 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1530 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1545 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1560 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1563 struct sumo_power_info *pi = sumo_get_pi(rdev);
1564 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1572 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1594 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1616 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1657 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1659 struct sumo_power_info *pi = sumo_get_pi(rdev);
1660 struct radeon_mode_info *mode_info = &rdev->mode_info;
1715 sumo_construct_display_voltage_mapping_table(rdev,
1718 sumo_construct_sclk_voltage_mapping_table(rdev,
1721 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1728 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1730 struct sumo_power_info *pi = sumo_get_pi(rdev);
1742 int sumo_dpm_init(struct radeon_device *rdev)
1751 rdev->pm.dpm.priv = pi;
1754 if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1765 if (rdev->family == CHIP_PALM)
1773 ret = sumo_parse_sys_info_table(rdev);
1777 sumo_construct_boot_and_acpi_state(rdev);
1779 ret = r600_get_platform_caps(rdev);
1783 ret = sumo_parse_power_table(rdev);
1796 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1809 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1811 r600_dpm_print_ps_status(rdev, rps);
1814 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1817 struct sumo_power_info *pi = sumo_get_pi(rdev);
1830 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1838 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1842 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev)
1844 struct sumo_power_info *pi = sumo_get_pi(rdev);
1863 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)
1865 struct sumo_power_info *pi = sumo_get_pi(rdev);
1870 void sumo_dpm_fini(struct radeon_device *rdev)
1874 sumo_cleanup_asic(rdev); /* ??? */
1876 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1877 kfree(rdev->pm.dpm.ps[i].ps_priv);
1879 kfree(rdev->pm.dpm.ps);
1880 kfree(rdev->pm.dpm.priv);
1883 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1885 struct sumo_power_info *pi = sumo_get_pi(rdev);
1894 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1896 struct sumo_power_info *pi = sumo_get_pi(rdev);
1901 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1904 struct sumo_power_info *pi = sumo_get_pi(rdev);
1914 sumo_enable_boost(rdev, rps, false);
1915 sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1916 sumo_set_forced_level(rdev, ps->num_levels - 1);
1917 sumo_set_forced_mode_enabled(rdev);
1919 sumo_power_level_enable(rdev, i, false);
1921 sumo_set_forced_mode(rdev, false);
1922 sumo_set_forced_mode_enabled(rdev);
1923 sumo_set_forced_mode(rdev, false);
1926 sumo_enable_boost(rdev, rps, false);
1927 sumo_power_level_enable(rdev, 0, true);
1928 sumo_set_forced_level(rdev, 0);
1929 sumo_set_forced_mode_enabled(rdev);
1931 sumo_power_level_enable(rdev, i, false);
1933 sumo_set_forced_mode(rdev, false);
1934 sumo_set_forced_mode_enabled(rdev);
1935 sumo_set_forced_mode(rdev, false);
1938 sumo_power_level_enable(rdev, i, true);
1941 sumo_enable_boost(rdev, rps, true);
1944 rdev->pm.dpm.forced_level = level;