Lines Matching refs:vddc
1756 s64 kt, kv, leakage_w, i_leakage, vddc;
1761 vddc = div64_s64(drm_int2fixp(v), 1000);
1770 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1773 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1775 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1794 s64 kt, kv, leakage_w, i_leakage, vddc;
1797 vddc = div64_s64(drm_int2fixp(v), 1000);
1801 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1803 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
2276 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2333 state->performance_levels[i-1].vddc, &vddc);
2337 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2342 state->performance_levels[i].vddc, &vddc);
2346 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2532 if (table->entries[i].vddc > *max)
2533 *max = table->entries[i].vddc;
2534 if (table->entries[i].vddc < *min)
2535 *min = table->entries[i].vddc;
2957 u16 vddc, vddci, min_vce_voltage = 0;
3015 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3016 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3024 if (ps->performance_levels[i].vddc > max_limits->vddc)
3025 ps->performance_levels[i].vddc = max_limits->vddc;
3074 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3077 vddc = ps->performance_levels[0].vddc;
3090 ps->performance_levels[0].vddc = vddc;
3101 ps->performance_levels[i].vddc = vddc;
3107 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3108 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3136 if (ps->performance_levels[i].vddc < min_vce_voltage)
3137 ps->performance_levels[i].vddc = min_vce_voltage;
3140 max_limits->vddc, &ps->performance_levels[i].vddc);
3146 max_limits->vddc, &ps->performance_levels[i].vddc);
3149 max_limits->vddc, &ps->performance_levels[i].vddc);
3154 max_limits->vddc, max_limits->vddci,
3155 &ps->performance_levels[i].vddc,
3161 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3219 u16 vddc, count = 0;
3223 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3225 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3226 si_pi->leakage_voltage.entries[count].voltage = vddc;
4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4152 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4174 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4403 initial_state->performance_levels[0].vddc,
4404 &table->initialState.levels[0].vddc);
4410 &table->initialState.levels[0].vddc,
4414 table->initialState.levels[0].vddc.index,
4427 initial_state->performance_levels[0].vddc,
4430 &table->initialState.levels[0].vddc);
4497 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4502 &table->ACPIState.levels[0].vddc, &std_vddc);
4505 table->ACPIState.levels[0].vddc.index,
4516 &table->ACPIState.levels[0].vddc);
4520 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4525 &table->ACPIState.levels[0].vddc, &std_vddc);
4529 table->ACPIState.levels[0].vddc.index,
4543 &table->ACPIState.levels[0].vddc);
4634 state->levels[0].std_vddc = state->levels[0].vddc;
4741 if (ulv->supported && ulv->pl.vddc) {
5029 pl->vddc, &level->vddc);
5034 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5039 level->vddc.index, &level->std_vddc);
5053 pl->vddc,
5056 &level->vddc);
5145 if (ulv->pl.vddc <
5282 if (ulv->supported && ulv->pl.vddc) {
5655 if (ulv->supported && ulv->pl.vddc != 0)
6733 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6741 /* patch up vddc if necessary */
6742 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6745 pl->vddc = leakage_voltage;
6748 pi->acpi_vddc = pl->vddc;
6764 if (pi->min_vddc_in_table > pl->vddc)
6765 pi->min_vddc_in_table = pl->vddc;
6767 if (pi->max_vddc_in_table < pl->vddc)
6768 pi->max_vddc_in_table = pl->vddc;
6772 u16 vddc, vddci, mvdd;
6773 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6776 pl->vddc = vddc;
6785 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7090 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7091 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);