Lines Matching defs:ulv
4617 struct si_ulv_param *ulv = &si_pi->ulv;
4621 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4630 if (ulv->one_pcie_lane_in_ulv)
4646 struct si_ulv_param *ulv = &si_pi->ulv;
4650 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4656 ulv->volt_change_delay);
4681 const struct si_ulv_param *ulv = &si_pi->ulv;
4741 if (ulv->supported && ulv->pl.vddc) {
4750 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4751 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5120 struct si_ulv_param *ulv = &si_pi->ulv;
5122 if (ulv->supported)
5133 const struct si_ulv_param *ulv = &si_pi->ulv;
5137 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5145 if (ulv->pl.vddc <
5161 const struct si_ulv_param *ulv = &si_pi->ulv;
5163 if (ulv->supported) {
5279 struct si_ulv_param *ulv = &si_pi->ulv;
5282 if (ulv->supported && ulv->pl.vddc) {
5638 struct si_ulv_param *ulv = &si_pi->ulv;
5655 if (ulv->supported && ulv->pl.vddc != 0)
5656 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
6756 si_pi->ulv.supported = false;
6757 si_pi->ulv.pl = *pl;
6758 si_pi->ulv.one_pcie_lane_in_ulv = false;
6759 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6760 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6761 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;