Lines Matching defs:tmp
1758 s64 tmp;
1770 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1771 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1772 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
2838 u32 tmp;
2874 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2876 spll_table->freq[i] = cpu_to_be32(tmp);
2878 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2880 spll_table->ss[i] = cpu_to_be32(tmp);
3191 u32 tmp, width, row, column, bank, density;
3194 tmp = RREG32(MC_SEQ_MISC0);
3195 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3196 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3197 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3202 tmp = RREG32(MC_ARB_RAMCFG);
3203 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3204 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3205 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3464 u32 tmp;
3470 &tmp, si_pi->sram_end);
3474 si_pi->state_table_start = tmp;
3479 &tmp, si_pi->sram_end);
3483 si_pi->soft_regs_start = tmp;
3488 &tmp, si_pi->sram_end);
3492 si_pi->mc_reg_table_start = tmp;
3497 &tmp, si_pi->sram_end);
3501 si_pi->fan_table_start = tmp;
3506 &tmp, si_pi->sram_end);
3510 si_pi->arb_table_start = tmp;
3515 &tmp, si_pi->sram_end);
3519 si_pi->cac_table_start = tmp;
3524 &tmp, si_pi->sram_end);
3528 si_pi->dte_table_start = tmp;
3533 &tmp, si_pi->sram_end);
3537 si_pi->spll_table_start = tmp;
3542 &tmp, si_pi->sram_end);
3546 si_pi->papm_cfg_table_start = tmp;
3655 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3658 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3666 u32 tmp, pipe;
3669 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3671 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3673 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3676 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3678 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3680 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3682 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3683 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3697 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3698 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3699 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3783 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3785 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3786 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3789 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3790 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3792 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4213 u32 tmp;
4216 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4220 tmp &= 0x00FFFFFF;
4221 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4223 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4240 u32 tmp;
4244 &tmp, si_pi->sram_end);
4248 tmp = (tmp >> 24) & 0xff;
4250 if (tmp == MC_CG_ARB_FREQ_F0)
4253 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4262 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4264 if (tmp >= 4)
4267 dram_rows = 1 << (tmp + 10);
4777 u64 tmp;
4790 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4791 do_div(tmp, reference_clock);
4792 fbdiv = (u32) tmp;
4899 u32 tmp;
4907 tmp = freq_nom / reference_clock;
4908 tmp = tmp * tmp;
4912 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5993 u32 tmp;
5996 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5997 si_pi->fan_ctrl_default_mode = tmp;
5998 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5999 si_pi->t_min = tmp;
6003 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6004 tmp |= TMIN(0);
6005 WREG32(CG_FDO_CTRL2, tmp);
6007 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6008 tmp |= FDO_PWM_MODE(mode);
6009 WREG32(CG_FDO_CTRL2, tmp);
6019 u32 reference_clock, tmp;
6072 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6073 fan_table.temp_src = (uint8_t)tmp;
6147 u32 tmp;
6169 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6170 tmp |= FDO_STATIC_DUTY(duty);
6171 WREG32(CG_FDO_CTRL0, tmp);
6195 u32 tmp;
6200 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6201 return (tmp >> FDO_PWM_MODE_SHIFT);
6229 u32 tach_period, tmp;
6246 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6247 tmp |= TARGET_PERIOD(tach_period);
6248 WREG32(CG_TACH_CTRL, tmp);
6259 u32 tmp;
6262 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6263 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6264 WREG32(CG_FDO_CTRL2, tmp);
6266 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6267 tmp |= TMIN(si_pi->t_min);
6268 WREG32(CG_FDO_CTRL2, tmp);
6283 u32 tmp;
6286 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6287 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6288 WREG32(CG_TACH_CTRL, tmp);
6291 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6292 tmp |= TACH_PWM_RESP_RATE(0x28);
6293 WREG32(CG_FDO_CTRL2, tmp);