Lines Matching defs:rdev
1720 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1721 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1722 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1725 extern int si_mc_load_microcode(struct radeon_device *rdev);
1726 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1728 static int si_populate_voltage_value(struct radeon_device *rdev,
1731 static int si_get_std_voltage_value(struct radeon_device *rdev,
1734 static int si_write_smc_soft_register(struct radeon_device *rdev,
1736 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1739 static int si_calculate_sclk_params(struct radeon_device *rdev,
1743 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1744 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1746 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1748 struct si_power_info *pi = rdev->pm.dpm.priv;
1780 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1808 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1819 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1822 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1823 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1849 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1851 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1852 struct si_power_info *si_pi = si_get_pi(rdev);
1855 if (rdev->family == CHIP_TAHITI) {
1862 switch (rdev->pdev->device) {
1889 } else if (rdev->family == CHIP_PITCAIRN) {
1890 switch (rdev->pdev->device) {
1926 } else if (rdev->family == CHIP_VERDE) {
1931 switch (rdev->pdev->device) {
1978 } else if (rdev->family == CHIP_OLAND) {
1979 switch (rdev->pdev->device) {
2028 } else if (rdev->family == CHIP_HAINAN) {
2051 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2075 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2080 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2087 xclk = radeon_get_xclk(rdev);
2105 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2113 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2116 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2119 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2120 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2122 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2123 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2124 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2138 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2141 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2142 struct si_power_info *si_pi = si_get_pi(rdev);
2147 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2148 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2158 ret = si_calculate_adjusted_tdp_limits(rdev,
2160 rdev->pm.dpm.tdp_adjustment,
2173 ret = si_copy_bytes_to_smc(rdev,
2192 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2203 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2206 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2207 struct si_power_info *si_pi = si_get_pi(rdev);
2211 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2217 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2219 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2221 ret = si_copy_bytes_to_smc(rdev,
2235 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2257 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2260 struct si_power_info *si_pi = si_get_pi(rdev);
2269 static int si_populate_power_containment_values(struct radeon_device *rdev,
2273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2274 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2297 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2332 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2337 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2341 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2346 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2350 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2363 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2367 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2379 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2401 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2420 static int si_enable_power_containment(struct radeon_device *rdev,
2424 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2430 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2431 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2440 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2450 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2452 struct si_power_info *si_pi = si_get_pi(rdev);
2508 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2515 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2518 struct si_power_info *si_pi = si_get_pi(rdev);
2520 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2560 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2565 struct si_power_info *si_pi = si_get_pi(rdev);
2573 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2581 si_calculate_leakage_for_v_and_t(rdev,
2600 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2604 struct si_power_info *si_pi = si_get_pi(rdev);
2611 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2616 si_calculate_leakage_for_v(rdev,
2635 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2637 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2638 struct si_power_info *si_pi = si_get_pi(rdev);
2644 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2657 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2660 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2665 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2675 ret = si_init_dte_leakage_table(rdev, cac_tables,
2679 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2684 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2700 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2706 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2719 static int si_program_cac_config_registers(struct radeon_device *rdev,
2758 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2760 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2761 struct si_power_info *si_pi = si_get_pi(rdev);
2768 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2774 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2781 static int si_enable_smc_cac(struct radeon_device *rdev,
2785 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2786 struct si_power_info *si_pi = si_get_pi(rdev);
2792 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2794 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2808 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2828 static int si_init_smc_spll_table(struct radeon_device *rdev)
2830 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2831 struct si_power_info *si_pi = si_get_pi(rdev);
2849 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2887 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2899 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2903 struct si_power_info *si_pi = si_get_pi(rdev);
2917 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2923 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2944 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2949 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2962 if (rdev->family == CHIP_HAINAN) {
2963 if ((rdev->pdev->revision == 0x81) ||
2964 (rdev->pdev->revision == 0xC3) ||
2965 (rdev->pdev->device == 0x6664) ||
2966 (rdev->pdev->device == 0x6665) ||
2967 (rdev->pdev->device == 0x6667)) {
2970 if ((rdev->pdev->revision == 0xC3) ||
2971 (rdev->pdev->device == 0x6665)) {
2975 } else if (rdev->family == CHIP_OLAND) {
2976 if ((rdev->pdev->revision == 0xC7) ||
2977 (rdev->pdev->revision == 0x80) ||
2978 (rdev->pdev->revision == 0x81) ||
2979 (rdev->pdev->revision == 0x83) ||
2980 (rdev->pdev->revision == 0x87) ||
2981 (rdev->pdev->device == 0x6604) ||
2982 (rdev->pdev->device == 0x6605)) {
2986 if (rdev->pm.dpm.high_pixelclock_count > 1)
2991 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2992 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2993 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3000 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3001 ni_dpm_vblank_too_short(rdev))
3009 if (rdev->pm.dpm.ac_power)
3010 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3012 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3018 if (rdev->pm.dpm.ac_power == false) {
3032 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3034 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3036 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3081 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3082 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3083 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3084 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3132 btc_adjust_clock_combinations(rdev, max_limits,
3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3141 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3144 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3147 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3148 rdev->clock.current_dispclk,
3153 btc_apply_voltage_delta_rules(rdev,
3161 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3167 static int si_read_smc_soft_register(struct radeon_device *rdev,
3170 struct si_power_info *si_pi = si_get_pi(rdev);
3172 return si_read_smc_sram_dword(rdev,
3178 static int si_write_smc_soft_register(struct radeon_device *rdev,
3181 struct si_power_info *si_pi = si_get_pi(rdev);
3183 return si_write_smc_sram_dword(rdev,
3188 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3209 if ((rdev->pdev->device == 0x6819) &&
3216 static void si_get_leakage_vddc(struct radeon_device *rdev)
3218 struct si_power_info *si_pi = si_get_pi(rdev);
3223 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3235 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3238 struct si_power_info *si_pi = si_get_pi(rdev);
3262 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3264 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3297 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3301 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3306 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3311 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3316 static void si_start_dpm(struct radeon_device *rdev)
3321 static void si_stop_dpm(struct radeon_device *rdev)
3326 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3336 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3342 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3351 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3353 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3358 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3361 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3368 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3372 return si_send_msg_to_smc(rdev, msg);
3375 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3377 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3380 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3384 int si_dpm_force_performance_level(struct radeon_device *rdev,
3387 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3395 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3398 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3401 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3404 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3407 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3411 rdev->pm.dpm.forced_level = level;
3417 static int si_set_boot_state(struct radeon_device *rdev)
3419 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3424 static int si_set_sw_state(struct radeon_device *rdev)
3426 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3430 static int si_halt_smc(struct radeon_device *rdev)
3432 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3435 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3439 static int si_resume_smc(struct radeon_device *rdev)
3441 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3444 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3448 static void si_dpm_start_smc(struct radeon_device *rdev)
3450 si_program_jump_on_start(rdev);
3451 si_start_smc(rdev);
3452 si_start_smc_clock(rdev);
3455 static void si_dpm_stop_smc(struct radeon_device *rdev)
3457 si_reset_smc(rdev);
3458 si_stop_smc_clock(rdev);
3461 static int si_process_firmware_header(struct radeon_device *rdev)
3463 struct si_power_info *si_pi = si_get_pi(rdev);
3467 ret = si_read_smc_sram_dword(rdev,
3476 ret = si_read_smc_sram_dword(rdev,
3485 ret = si_read_smc_sram_dword(rdev,
3494 ret = si_read_smc_sram_dword(rdev,
3503 ret = si_read_smc_sram_dword(rdev,
3512 ret = si_read_smc_sram_dword(rdev,
3521 ret = si_read_smc_sram_dword(rdev,
3530 ret = si_read_smc_sram_dword(rdev,
3539 ret = si_read_smc_sram_dword(rdev,
3551 static void si_read_clock_registers(struct radeon_device *rdev)
3553 struct si_power_info *si_pi = si_get_pi(rdev);
3572 static void si_enable_thermal_protection(struct radeon_device *rdev,
3581 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3587 static int si_enter_ulp_state(struct radeon_device *rdev)
3596 static int si_exit_ulp_state(struct radeon_device *rdev)
3604 for (i = 0; i < rdev->usec_timeout; i++) {
3614 static int si_notify_smc_display_change(struct radeon_device *rdev,
3620 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3624 static void si_program_response_times(struct radeon_device *rdev)
3630 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3632 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3640 reference_clock = radeon_get_xclk(rdev);
3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3647 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3648 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3649 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3652 static void si_program_ds_registers(struct radeon_device *rdev)
3654 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3664 static void si_program_display_gap(struct radeon_device *rdev)
3670 if (rdev->pm.dpm.new_active_crtc_count > 0)
3675 if (rdev->pm.dpm.new_active_crtc_count > 1)
3685 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3686 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3688 for (i = 0; i < rdev->num_crtc; i++) {
3689 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3692 if (i == rdev->num_crtc)
3706 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3709 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3711 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3722 static void si_setup_bsp(struct radeon_device *rdev)
3724 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3725 u32 xclk = radeon_get_xclk(rdev);
3746 static void si_program_git(struct radeon_device *rdev)
3751 static void si_program_tp(struct radeon_device *rdev)
3771 static void si_program_tpp(struct radeon_device *rdev)
3776 static void si_program_sstp(struct radeon_device *rdev)
3781 static void si_enable_display_gap(struct radeon_device *rdev)
3795 static void si_program_vc(struct radeon_device *rdev)
3797 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3802 static void si_clear_vc(struct radeon_device *rdev)
3842 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3844 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3862 static int si_upload_firmware(struct radeon_device *rdev)
3864 struct si_power_info *si_pi = si_get_pi(rdev);
3867 si_reset_smc(rdev);
3868 si_stop_smc_clock(rdev);
3870 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3875 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3902 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3919 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3940 static int si_construct_voltage_tables(struct radeon_device *rdev)
3942 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3943 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3944 struct si_power_info *si_pi = si_get_pi(rdev);
3948 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3954 si_trim_voltage_table_to_fit_state_table(rdev,
3958 ret = si_get_svi2_voltage_table(rdev,
3959 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3968 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3974 si_trim_voltage_table_to_fit_state_table(rdev,
3979 ret = si_get_svi2_voltage_table(rdev,
3980 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3987 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4001 si_trim_voltage_table_to_fit_state_table(rdev,
4007 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4020 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4030 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4033 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4034 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4035 struct si_power_info *si_pi = si_get_pi(rdev);
4039 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4041 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4043 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4047 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4060 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4068 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4075 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4076 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4077 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4082 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4093 static int si_populate_voltage_value(struct radeon_device *rdev,
4113 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4116 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4117 struct si_power_info *si_pi = si_get_pi(rdev);
4130 static int si_get_std_voltage_value(struct radeon_device *rdev,
4138 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4139 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4140 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4143 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4145 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4147 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4152 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4158 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4160 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4162 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4173 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4174 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4181 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4191 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4210 static int si_init_arb_table_index(struct radeon_device *rdev)
4212 struct si_power_info *si_pi = si_get_pi(rdev);
4216 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4223 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4226 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4228 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4231 static int si_reset_to_default(struct radeon_device *rdev)
4233 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4237 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4239 struct si_power_info *si_pi = si_get_pi(rdev);
4243 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4253 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4256 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4275 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4284 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4286 radeon_atom_set_engine_dram_timings(rdev,
4301 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4305 struct si_power_info *si_pi = si_get_pi(rdev);
4311 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4314 ret = si_copy_bytes_to_smc(rdev,
4328 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4331 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4335 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4338 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4339 struct si_power_info *si_pi = si_get_pi(rdev);
4342 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4348 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4353 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4354 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4355 struct si_power_info *si_pi = si_get_pi(rdev);
4402 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4409 ret = si_get_std_voltage_value(rdev,
4413 si_populate_std_voltage_value(rdev, std_vddc,
4419 si_populate_voltage_value(rdev,
4425 si_populate_phase_shedding_value(rdev,
4426 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4432 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4443 si_get_strobe_mode_settings(rdev,
4471 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4474 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4475 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4476 struct si_power_info *si_pi = si_get_pi(rdev);
4496 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4501 ret = si_get_std_voltage_value(rdev,
4504 si_populate_std_voltage_value(rdev, std_vddc,
4511 si_populate_phase_shedding_value(rdev,
4512 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4519 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4524 ret = si_get_std_voltage_value(rdev,
4528 si_populate_std_voltage_value(rdev, std_vddc,
4532 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4538 si_populate_phase_shedding_value(rdev,
4539 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4548 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4592 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4612 static int si_populate_ulv_state(struct radeon_device *rdev,
4615 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4616 struct si_power_info *si_pi = si_get_pi(rdev);
4621 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4643 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4645 struct si_power_info *si_pi = si_get_pi(rdev);
4650 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4655 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4658 ret = si_copy_bytes_to_smc(rdev,
4669 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4671 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4676 static int si_init_smc_table(struct radeon_device *rdev)
4678 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4679 struct si_power_info *si_pi = si_get_pi(rdev);
4680 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4687 si_populate_smc_voltage_tables(rdev, table);
4689 switch (rdev->pm.int_thermal_type) {
4702 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4705 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4706 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4710 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4719 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4721 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4722 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4726 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4730 ret = si_populate_smc_acpi_state(rdev, table);
4736 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4742 ret = si_populate_ulv_state(rdev, &table->ULVState);
4746 ret = si_program_ulv_memory_timing_parameters(rdev);
4753 lane_width = radeon_get_pcie_lanes(rdev);
4754 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4759 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4764 static int si_calculate_sclk_params(struct radeon_device *rdev,
4768 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4769 struct si_power_info *si_pi = si_get_pi(rdev);
4778 u32 reference_clock = rdev->clock.spll.reference_freq;
4783 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4809 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4834 static int si_populate_sclk_value(struct radeon_device *rdev,
4841 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4855 static int si_populate_mclk_value(struct radeon_device *rdev,
4862 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4863 struct si_power_info *si_pi = si_get_pi(rdev);
4876 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4900 u32 reference_clock = rdev->clock.mpll.reference_freq;
4909 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4944 static void si_populate_smc_sp(struct radeon_device *rdev,
4949 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4959 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4963 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4965 struct si_power_info *si_pi = si_get_pi(rdev);
4977 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4987 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5001 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5013 level->strobeMode = si_get_strobe_mode_settings(rdev,
5019 ret = si_populate_mclk_value(rdev,
5027 ret = si_populate_voltage_value(rdev,
5034 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5038 ret = si_populate_std_voltage_value(rdev, std_vddc,
5044 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5051 ret = si_populate_phase_shedding_value(rdev,
5052 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5063 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5068 static int si_populate_smc_t(struct radeon_device *rdev,
5072 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5117 static int si_disable_ulv(struct radeon_device *rdev)
5119 struct si_power_info *si_pi = si_get_pi(rdev);
5123 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5129 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5132 const struct si_power_info *si_pi = si_get_pi(rdev);
5142 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5143 if (rdev->clock.current_dispclk <=
5144 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5146 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5157 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5160 const struct si_power_info *si_pi = si_get_pi(rdev);
5164 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5165 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5171 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5175 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5176 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5177 struct si_power_info *si_pi = si_get_pi(rdev);
5210 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5234 si_write_smc_soft_register(rdev,
5238 si_populate_smc_sp(rdev, radeon_state, smc_state);
5240 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5244 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5248 return si_populate_smc_t(rdev, radeon_state, smc_state);
5251 static int si_upload_sw_state(struct radeon_device *rdev,
5254 struct si_power_info *si_pi = si_get_pi(rdev);
5266 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5270 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5276 static int si_upload_ulv_state(struct radeon_device *rdev)
5278 struct si_power_info *si_pi = si_get_pi(rdev);
5290 ret = si_populate_ulv_state(rdev, smc_state);
5292 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5299 static int si_upload_smc_data(struct radeon_device *rdev)
5304 if (rdev->pm.dpm.new_active_crtc_count == 0)
5307 for (i = 0; i < rdev->num_crtc; i++) {
5308 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5309 radeon_crtc = rdev->mode_info.crtcs[i];
5320 if (si_write_smc_soft_register(rdev,
5325 if (si_write_smc_soft_register(rdev,
5330 if (si_write_smc_soft_register(rdev,
5338 static int si_set_mc_special_registers(struct radeon_device *rdev,
5341 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5515 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5517 struct si_power_info *si_pi = si_get_pi(rdev);
5520 u8 module_index = rv770_get_memory_module_index(rdev);
5542 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5552 ret = si_set_mc_special_registers(rdev, si_table);
5565 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5568 struct si_power_info *si_pi = si_get_pi(rdev);
5599 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5603 struct si_power_info *si_pi = si_get_pi(rdev);
5619 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5627 si_convert_mc_reg_table_entry_to_smc(rdev,
5633 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5637 struct si_power_info *si_pi = si_get_pi(rdev);
5643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5645 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5647 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5656 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5664 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5666 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5671 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5675 struct si_power_info *si_pi = si_get_pi(rdev);
5683 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5686 return si_copy_bytes_to_smc(rdev, address,
5693 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5701 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5716 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5726 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5730 struct si_power_info *si_pi = si_get_pi(rdev);
5731 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5735 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5745 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5752 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5757 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5766 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5770 struct si_power_info *si_pi = si_get_pi(rdev);
5771 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5783 (si_get_current_pcie_speed(rdev) > 0))
5787 radeon_acpi_pcie_performance_request(rdev, request, false);
5793 static int si_ds_request(struct radeon_device *rdev,
5796 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5800 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5804 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5811 static void si_set_max_cu_value(struct radeon_device *rdev)
5813 struct si_power_info *si_pi = si_get_pi(rdev);
5815 if (rdev->family == CHIP_VERDE) {
5816 switch (rdev->pdev->device) {
5852 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5861 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5883 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5887 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5889 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5890 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5891 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5892 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5896 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5907 radeon_set_pcie_lanes(rdev, new_lane_width);
5908 lane_width = radeon_get_pcie_lanes(rdev);
5909 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5913 static void si_set_vce_clock(struct radeon_device *rdev,
5921 vce_v1_0_enable_mgcg(rdev, false);
5923 vce_v1_0_enable_mgcg(rdev, true);
5924 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5928 void si_dpm_setup_asic(struct radeon_device *rdev)
5932 r = si_mc_load_microcode(rdev);
5935 rv770_get_memory_type(rdev);
5936 si_read_clock_registers(rdev);
5937 si_enable_acpi_power_management(rdev);
5940 static int si_thermal_enable_alert(struct radeon_device *rdev,
5950 rdev->irq.dpm_thermal = false;
5951 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5959 rdev->irq.dpm_thermal = true;
5965 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5984 rdev->pm.dpm.thermal.min_temp = low_temp;
5985 rdev->pm.dpm.thermal.max_temp = high_temp;
5990 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5992 struct si_power_info *si_pi = si_get_pi(rdev);
6012 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6014 struct si_power_info *si_pi = si_get_pi(rdev);
6024 rdev->pm.dpm.fan.ucode_fan_control = false;
6031 rdev->pm.dpm.fan.ucode_fan_control = false;
6035 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6039 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6040 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6042 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6043 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6048 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6049 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6050 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6057 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6065 reference_clock = radeon_get_xclk(rdev);
6067 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6075 ret = si_copy_bytes_to_smc(rdev,
6083 rdev->pm.dpm.fan.ucode_fan_control = false;
6089 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6091 struct si_power_info *si_pi = si_get_pi(rdev);
6094 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6103 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6105 struct si_power_info *si_pi = si_get_pi(rdev);
6108 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6118 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6124 if (rdev->pm.no_fan)
6143 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6146 struct si_power_info *si_pi = si_get_pi(rdev);
6151 if (rdev->pm.no_fan)
6176 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6180 if (rdev->pm.dpm.fan.ucode_fan_control)
6181 si_fan_ctrl_stop_smc_fan_control(rdev);
6182 si_fan_ctrl_set_static_mode(rdev, mode);
6185 if (rdev->pm.dpm.fan.ucode_fan_control)
6186 si_thermal_start_smc_fan_control(rdev);
6188 si_fan_ctrl_set_default_mode(rdev);
6192 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6194 struct si_power_info *si_pi = si_get_pi(rdev);
6205 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6209 u32 xclk = radeon_get_xclk(rdev);
6211 if (rdev->pm.no_fan)
6214 if (rdev->pm.fan_pulses_per_revolution == 0)
6226 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6230 u32 xclk = radeon_get_xclk(rdev);
6232 if (rdev->pm.no_fan)
6235 if (rdev->pm.fan_pulses_per_revolution == 0)
6238 if ((speed < rdev->pm.fan_min_rpm) ||
6239 (speed > rdev->pm.fan_max_rpm))
6242 if (rdev->pm.dpm.fan.ucode_fan_control)
6243 si_fan_ctrl_stop_smc_fan_control(rdev);
6250 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6256 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6258 struct si_power_info *si_pi = si_get_pi(rdev);
6273 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6275 if (rdev->pm.dpm.fan.ucode_fan_control) {
6276 si_fan_ctrl_start_smc_fan_control(rdev);
6277 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6281 static void si_thermal_initialize(struct radeon_device *rdev)
6285 if (rdev->pm.fan_pulses_per_revolution) {
6287 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6296 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6300 si_thermal_initialize(rdev);
6301 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6304 ret = si_thermal_enable_alert(rdev, true);
6307 if (rdev->pm.dpm.fan.ucode_fan_control) {
6308 ret = si_halt_smc(rdev);
6311 ret = si_thermal_setup_fan_table(rdev);
6314 ret = si_resume_smc(rdev);
6317 si_thermal_start_smc_fan_control(rdev);
6323 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6325 if (!rdev->pm.no_fan) {
6326 si_fan_ctrl_set_default_mode(rdev);
6327 si_fan_ctrl_stop_smc_fan_control(rdev);
6331 int si_dpm_enable(struct radeon_device *rdev)
6333 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6334 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6335 struct si_power_info *si_pi = si_get_pi(rdev);
6336 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6339 if (si_is_smc_running(rdev))
6342 si_enable_voltage_control(rdev, true);
6344 si_get_mvdd_configuration(rdev);
6346 ret = si_construct_voltage_tables(rdev);
6353 ret = si_initialize_mc_reg_table(rdev);
6358 si_enable_spread_spectrum(rdev, true);
6360 si_enable_thermal_protection(rdev, true);
6361 si_setup_bsp(rdev);
6362 si_program_git(rdev);
6363 si_program_tp(rdev);
6364 si_program_tpp(rdev);
6365 si_program_sstp(rdev);
6366 si_enable_display_gap(rdev);
6367 si_program_vc(rdev);
6368 ret = si_upload_firmware(rdev);
6373 ret = si_process_firmware_header(rdev);
6378 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6383 ret = si_init_smc_table(rdev);
6388 ret = si_init_smc_spll_table(rdev);
6393 ret = si_init_arb_table_index(rdev);
6399 ret = si_populate_mc_reg_table(rdev, boot_ps);
6405 ret = si_initialize_smc_cac_tables(rdev);
6410 ret = si_initialize_hardware_cac_manager(rdev);
6415 ret = si_initialize_smc_dte_tables(rdev);
6420 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6425 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6430 si_program_response_times(rdev);
6431 si_program_ds_registers(rdev);
6432 si_dpm_start_smc(rdev);
6433 ret = si_notify_smc_display_change(rdev, false);
6438 si_enable_sclk_control(rdev, true);
6439 si_start_dpm(rdev);
6441 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6443 si_thermal_start_thermal_controller(rdev);
6445 ni_update_current_ps(rdev, boot_ps);
6450 static int si_set_temperature_range(struct radeon_device *rdev)
6454 ret = si_thermal_enable_alert(rdev, false);
6457 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6460 ret = si_thermal_enable_alert(rdev, true);
6467 int si_dpm_late_enable(struct radeon_device *rdev)
6471 ret = si_set_temperature_range(rdev);
6478 void si_dpm_disable(struct radeon_device *rdev)
6480 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6481 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6483 if (!si_is_smc_running(rdev))
6485 si_thermal_stop_thermal_controller(rdev);
6486 si_disable_ulv(rdev);
6487 si_clear_vc(rdev);
6489 si_enable_thermal_protection(rdev, false);
6490 si_enable_power_containment(rdev, boot_ps, false);
6491 si_enable_smc_cac(rdev, boot_ps, false);
6492 si_enable_spread_spectrum(rdev, false);
6493 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6494 si_stop_dpm(rdev);
6495 si_reset_to_default(rdev);
6496 si_dpm_stop_smc(rdev);
6497 si_force_switch_to_arb_f0(rdev);
6499 ni_update_current_ps(rdev, boot_ps);
6502 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6504 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6505 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6508 ni_update_requested_ps(rdev, new_ps);
6510 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6515 static int si_power_control_set_level(struct radeon_device *rdev)
6517 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6520 ret = si_restrict_performance_levels_before_switch(rdev);
6523 ret = si_halt_smc(rdev);
6526 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6529 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6532 ret = si_resume_smc(rdev);
6535 ret = si_set_sw_state(rdev);
6541 int si_dpm_set_power_state(struct radeon_device *rdev)
6543 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6548 ret = si_disable_ulv(rdev);
6553 ret = si_restrict_performance_levels_before_switch(rdev);
6559 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6560 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6561 ret = si_enable_power_containment(rdev, new_ps, false);
6566 ret = si_enable_smc_cac(rdev, new_ps, false);
6571 ret = si_halt_smc(rdev);
6576 ret = si_upload_sw_state(rdev, new_ps);
6581 ret = si_upload_smc_data(rdev);
6586 ret = si_upload_ulv_state(rdev);
6592 ret = si_upload_mc_reg_table(rdev, new_ps);
6598 ret = si_program_memory_timing_parameters(rdev, new_ps);
6603 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6605 ret = si_resume_smc(rdev);
6610 ret = si_set_sw_state(rdev);
6615 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6616 si_set_vce_clock(rdev, new_ps, old_ps);
6618 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6619 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6624 ret = si_enable_smc_cac(rdev, new_ps, true);
6629 ret = si_enable_power_containment(rdev, new_ps, true);
6635 ret = si_power_control_set_level(rdev);
6644 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6646 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6649 ni_update_current_ps(rdev, new_ps);
6653 void si_dpm_reset_asic(struct radeon_device *rdev)
6655 si_restrict_performance_levels_before_switch(rdev);
6656 si_disable_ulv(rdev);
6657 si_set_boot_state(rdev);
6661 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6663 si_program_display_gap(rdev);
6688 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6709 rdev->pm.dpm.boot_ps = rps;
6711 rdev->pm.dpm.uvd_ps = rps;
6714 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6718 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6719 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6720 struct si_power_info *si_pi = si_get_pi(rdev);
6736 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6742 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6773 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6774 pl->mclk = rdev->clock.default_mclk;
6775 pl->sclk = rdev->clock.default_sclk;
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6784 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6785 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6786 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6790 static int si_parse_power_table(struct radeon_device *rdev)
6792 struct radeon_mode_info *mode_info = &rdev->mode_info;
6822 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
6825 if (!rdev->pm.dpm.ps)
6834 if (!rdev->pm.power_state[i].clock_info)
6838 kfree(rdev->pm.dpm.ps);
6841 rdev->pm.dpm.ps[i].ps_priv = ps;
6842 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6856 si_parse_pplib_clock_info(rdev,
6857 &rdev->pm.dpm.ps[i], k,
6863 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6868 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6875 rdev->pm.dpm.vce_states[i].sclk = sclk;
6876 rdev->pm.dpm.vce_states[i].mclk = mclk;
6882 int si_dpm_init(struct radeon_device *rdev)
6890 struct pci_dev *root = rdev->pdev->bus->self;
6896 rdev->pm.dpm.priv = si_pi;
6901 if (!pci_is_root_bus(rdev->pdev->bus))
6917 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6919 si_set_max_cu_value(rdev);
6921 rv770_get_max_vddc(rdev);
6922 si_get_leakage_vddc(rdev);
6923 si_patch_dependency_tables_based_on_leakage(rdev);
6930 ret = r600_get_platform_caps(rdev);
6934 ret = r600_parse_extended_power_table(rdev);
6938 ret = si_parse_power_table(rdev);
6942 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6946 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6947 r600_free_extended_power_table(rdev);
6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6957 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6960 if (rdev->pm.dpm.voltage_response_time == 0)
6961 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6962 if (rdev->pm.dpm.backbias_response_time == 0)
6963 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6965 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6975 if (si_is_special_1gb_platform(rdev))
6985 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6989 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6992 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6997 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7001 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7005 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7009 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7012 rv770_get_engine_memory_ss(rdev);
7023 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7033 radeon_acpi_is_pcie_performance_request_supported(rdev);
7040 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7041 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7042 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7043 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7044 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7045 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7046 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7048 si_initialize_powertune_defaults(rdev);
7051 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7052 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7053 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7054 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7061 void si_dpm_fini(struct radeon_device *rdev)
7065 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7066 kfree(rdev->pm.dpm.ps[i].ps_priv);
7068 kfree(rdev->pm.dpm.ps);
7069 kfree(rdev->pm.dpm.priv);
7070 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7071 r600_free_extended_power_table(rdev);
7074 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7077 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7095 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7097 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7113 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7115 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);