Lines Matching defs:levels
2299 smc_state->levels[0].dpm2.MaxPS = 0;
2300 smc_state->levels[0].dpm2.NearTDPDec = 0;
2301 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2302 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2303 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2353 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2354 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2355 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2356 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2357 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2413 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2414 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
3389 u32 levels = ps->performance_level_count;
3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3407 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
4359 table->initialState.levels[0].mclk.vDLL_CNTL =
4361 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4363 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4365 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4367 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4369 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4371 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4373 table->initialState.levels[0].mclk.vMPLL_SS =
4375 table->initialState.levels[0].mclk.vMPLL_SS2 =
4378 table->initialState.levels[0].mclk.mclk_value =
4381 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4383 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4385 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4387 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4389 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4391 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4394 table->initialState.levels[0].sclk.sclk_value =
4397 table->initialState.levels[0].arbRefreshState =
4400 table->initialState.levels[0].ACIndex = 0;
4404 &table->initialState.levels[0].vddc);
4410 &table->initialState.levels[0].vddc,
4414 table->initialState.levels[0].vddc.index,
4415 &table->initialState.levels[0].std_vddc);
4422 &table->initialState.levels[0].vddci);
4430 &table->initialState.levels[0].vddc);
4432 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4435 table->initialState.levels[0].aT = cpu_to_be32(reg);
4437 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4439 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4442 table->initialState.levels[0].strobeMode =
4447 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4449 table->initialState.levels[0].mcFlags = 0;
4456 table->initialState.levels[0].dpm2.MaxPS = 0;
4457 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4458 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4459 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4460 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4463 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4466 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4497 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4502 &table->ACPIState.levels[0].vddc, &std_vddc);
4505 table->ACPIState.levels[0].vddc.index,
4506 &table->ACPIState.levels[0].std_vddc);
4508 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4516 &table->ACPIState.levels[0].vddc);
4520 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4525 &table->ACPIState.levels[0].vddc, &std_vddc);
4529 table->ACPIState.levels[0].vddc.index,
4530 &table->ACPIState.levels[0].std_vddc);
4532 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4543 &table->ACPIState.levels[0].vddc);
4550 &table->ACPIState.levels[0].vddci);
4561 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4563 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4565 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4567 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4569 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4571 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4573 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4575 table->ACPIState.levels[0].mclk.vMPLL_SS =
4577 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4580 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4582 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4584 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4586 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4589 table->ACPIState.levels[0].mclk.mclk_value = 0;
4590 table->ACPIState.levels[0].sclk.sclk_value = 0;
4592 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4595 table->ACPIState.levels[0].ACIndex = 0;
4597 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4598 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4599 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4600 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4601 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4604 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4607 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4622 &state->levels[0]);
4626 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4628 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4632 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4633 state->levels[0].ACIndex = 1;
4634 state->levels[0].std_vddc = state->levels[0].vddc;
4953 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4955 smc_state->levels[ps->performance_level_count - 1].bSP =
5084 smc_state->levels[0].aT = cpu_to_be32(a_t);
5088 smc_state->levels[0].aT = cpu_to_be32(0);
5104 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5106 smc_state->levels[i].aT = cpu_to_be32(a_t);
5111 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5204 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5206 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5211 &smc_state->levels[i]);
5212 smc_state->levels[i].arbRefreshState =
5219 smc_state->levels[i].displayWatermark =
5223 smc_state->levels[i].displayWatermark = (i < 2) ?
5227 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5229 smc_state->levels[i].ACIndex = 0;