Lines Matching defs:tmp
1346 u32 tmp;
1348 tmp = RREG32(CG_CLKPIN_CNTL_2);
1349 if (tmp & MUX_TCLK_TO_XCLK)
1352 tmp = RREG32(CG_CLKPIN_CNTL);
1353 if (tmp & XTALIN_DIVIDE)
1976 u32 tmp, buffer_alloc, i;
1993 tmp = 0; /* 1/2 */
1996 tmp = 2; /* whole */
2000 tmp = 0;
2005 DC_LB_MEMORY_CONFIG(tmp));
2017 switch (tmp) {
2032 u32 tmp = RREG32(MC_SHARED_CHMAP);
2034 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2216 u32 tmp, dmif_size = 12288;
2235 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
2236 tmp = min(dfixed_trunc(a), tmp);
2238 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
2311 u32 tmp, arb_control3;
2436 tmp = arb_control3;
2437 tmp &= ~LATENCY_WATERMARK_MASK(3);
2438 tmp |= LATENCY_WATERMARK_MASK(1);
2439 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2444 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2445 tmp &= ~LATENCY_WATERMARK_MASK(3);
2446 tmp |= LATENCY_WATERMARK_MASK(2);
2447 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
3099 u32 tmp;
3213 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3214 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3347 tmp = RREG32(HDP_MISC_CNTL);
3348 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3349 WREG32(HDP_MISC_CNTL, tmp);
3655 u32 tmp;
3674 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3676 tmp |= BUF_SWAP_32BIT;
3678 WREG32(CP_RB0_CNTL, tmp);
3681 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3692 tmp |= RB_NO_UPDATE;
3697 WREG32(CP_RB0_CNTL, tmp);
3705 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3707 tmp |= BUF_SWAP_32BIT;
3709 WREG32(CP_RB1_CNTL, tmp);
3712 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3721 WREG32(CP_RB1_CNTL, tmp);
3729 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3731 tmp |= BUF_SWAP_32BIT;
3733 WREG32(CP_RB2_CNTL, tmp);
3736 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3745 WREG32(CP_RB2_CNTL, tmp);
3781 u32 tmp;
3784 tmp = RREG32(GRBM_STATUS);
3785 if (tmp & (PA_BUSY | SC_BUSY |
3793 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3797 if (tmp & GRBM_EE_BUSY)
3801 tmp = RREG32(GRBM_STATUS2);
3802 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3806 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3807 if (!(tmp & DMA_IDLE))
3811 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3812 if (!(tmp & DMA_IDLE))
3816 tmp = RREG32(SRBM_STATUS2);
3817 if (tmp & DMA_BUSY)
3820 if (tmp & DMA1_BUSY)
3824 tmp = RREG32(SRBM_STATUS);
3826 if (tmp & IH_BUSY)
3829 if (tmp & SEM_BUSY)
3832 if (tmp & GRBM_RQ_PENDING)
3835 if (tmp & VMC_BUSY)
3838 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3846 tmp = RREG32(VM_L2_STATUS);
3847 if (tmp & L2_BUSY)
3863 u32 tmp;
3888 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3889 tmp &= ~DMA_RB_ENABLE;
3890 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3894 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3895 tmp &= ~DMA_RB_ENABLE;
3896 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3955 tmp = RREG32(GRBM_SOFT_RESET);
3956 tmp |= grbm_soft_reset;
3957 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3958 WREG32(GRBM_SOFT_RESET, tmp);
3959 tmp = RREG32(GRBM_SOFT_RESET);
3963 tmp &= ~grbm_soft_reset;
3964 WREG32(GRBM_SOFT_RESET, tmp);
3965 tmp = RREG32(GRBM_SOFT_RESET);
3969 tmp = RREG32(SRBM_SOFT_RESET);
3970 tmp |= srbm_soft_reset;
3971 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3972 WREG32(SRBM_SOFT_RESET, tmp);
3973 tmp = RREG32(SRBM_SOFT_RESET);
3977 tmp &= ~srbm_soft_reset;
3978 WREG32(SRBM_SOFT_RESET, tmp);
3979 tmp = RREG32(SRBM_SOFT_RESET);
3993 u32 tmp, i;
3995 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3996 tmp |= SPLL_BYPASS_EN;
3997 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3999 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4000 tmp |= SPLL_CTLREQ_CHG;
4001 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
4009 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4010 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
4011 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
4013 tmp = RREG32(MPLL_CNTL_MODE);
4014 tmp &= ~MPLL_MCLK_SEL;
4015 WREG32(MPLL_CNTL_MODE, tmp);
4020 u32 tmp;
4022 tmp = RREG32(SPLL_CNTL_MODE);
4023 tmp |= SPLL_SW_DIR_CONTROL;
4024 WREG32(SPLL_CNTL_MODE, tmp);
4026 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4027 tmp |= SPLL_RESET;
4028 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4030 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4031 tmp |= SPLL_SLEEP;
4032 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4034 tmp = RREG32(SPLL_CNTL_MODE);
4035 tmp &= ~SPLL_SW_DIR_CONTROL;
4036 WREG32(SPLL_CNTL_MODE, tmp);
4042 u32 tmp, i;
4055 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4056 tmp &= ~DMA_RB_ENABLE;
4057 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4059 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
4060 tmp &= ~DMA_RB_ENABLE;
4061 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
4148 u32 tmp;
4175 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
4176 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
4177 WREG32(MC_VM_FB_LOCATION, tmp);
4212 u32 tmp;
4217 tmp = RREG32(MC_ARB_RAMCFG);
4218 if (tmp & CHANSIZE_OVERRIDE) {
4220 } else if (tmp & CHANSIZE_MASK) {
4225 tmp = RREG32(MC_SHARED_CHMAP);
4226 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
4261 tmp = RREG32(CONFIG_MEMSIZE);
4263 if (tmp & 0xffff0000) {
4264 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
4265 if (tmp & 0xffff)
4266 tmp &= 0xffff;
4268 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
5152 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5157 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5159 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5160 WREG32(CP_INT_CNTL_RING0, tmp);
5164 tmp = RREG32(DB_DEPTH_INFO);
5178 u32 tmp, tmp2;
5180 tmp = RREG32(UVD_CGC_CTRL);
5181 tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
5182 tmp |= DCM | CG_DT(1) | CLK_OD(4);
5185 tmp &= ~0x7ffff800;
5188 tmp |= 0x7ffff800;
5192 WREG32(UVD_CGC_CTRL, tmp);
5203 u32 tmp = RREG32(UVD_CGC_CTRL);
5204 tmp &= ~DCM;
5205 WREG32(UVD_CGC_CTRL, tmp);
5227 u32 tmp;
5229 tmp = RREG32(RLC_CNTL);
5230 if (tmp != rlc)
5249 u32 tmp;
5254 for (tmp = 0; tmp < 5; tmp++)
5261 u32 tmp;
5264 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
5265 WREG32(RLC_TTOP_D, tmp);
5267 tmp = RREG32(RLC_PG_CNTL);
5268 tmp |= GFX_PG_ENABLE;
5269 WREG32(RLC_PG_CNTL, tmp);
5271 tmp = RREG32(RLC_AUTO_PG_CTRL);
5272 tmp |= AUTO_PG_EN;
5273 WREG32(RLC_AUTO_PG_CTRL, tmp);
5275 tmp = RREG32(RLC_AUTO_PG_CTRL);
5276 tmp &= ~AUTO_PG_EN;
5277 WREG32(RLC_AUTO_PG_CTRL, tmp);
5279 tmp = RREG32(DB_RENDER_CONTROL);
5285 u32 tmp;
5289 tmp = RREG32(RLC_PG_CNTL);
5290 tmp |= GFX_PG_SRC;
5291 WREG32(RLC_PG_CNTL, tmp);
5295 tmp = RREG32(RLC_AUTO_PG_CTRL);
5297 tmp &= ~GRBM_REG_SGIT_MASK;
5298 tmp |= GRBM_REG_SGIT(0x700);
5299 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
5300 WREG32(RLC_AUTO_PG_CTRL, tmp);
5305 u32 mask = 0, tmp, tmp1;
5309 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
5313 tmp &= 0xffff0000;
5315 tmp |= tmp1;
5316 tmp >>= 16;
5323 return (~tmp) & mask;
5330 u32 tmp = 0;
5347 tmp |= (cu_bitmap << (i * 16 + j * 8));
5351 WREG32(RLC_PG_AO_CU_MASK, tmp);
5353 tmp = RREG32(RLC_MAX_PG_CU);
5354 tmp &= ~MAX_PU_CU_MASK;
5355 tmp |= MAX_PU_CU(active_cu_number);
5356 WREG32(RLC_MAX_PG_CU, tmp);
5362 u32 data, orig, tmp;
5371 tmp = si_halt_rlc(rdev);
5379 si_update_rlc(rdev, tmp);
5402 u32 data, orig, tmp = 0;
5422 tmp = si_halt_rlc(rdev);
5428 si_update_rlc(rdev, tmp);
5445 tmp = si_halt_rlc(rdev);
5451 si_update_rlc(rdev, tmp);
5458 u32 orig, data, tmp;
5461 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5462 tmp |= 0x3fff;
5463 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5473 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5474 tmp &= ~0x3fff;
5475 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5813 u32 tmp = RREG32(GRBM_SOFT_RESET);
5815 tmp |= SOFT_RESET_RLC;
5816 WREG32(GRBM_SOFT_RESET, tmp);
5818 tmp &= ~SOFT_RESET_RLC;
5819 WREG32(GRBM_SOFT_RESET, tmp);
5843 u32 tmp;
5846 tmp = RREG32(MC_SEQ_MISC0);
5847 if ((tmp & 0xF0000000) == 0xB0000000)
5854 u32 tmp;
5856 tmp = RREG32(RLC_LB_CNTL);
5858 tmp |= LOAD_BALANCE_ENABLE;
5860 tmp &= ~LOAD_BALANCE_ENABLE;
5861 WREG32(RLC_LB_CNTL, tmp);
5955 u32 tmp;
5957 tmp = RREG32(CP_INT_CNTL_RING0) &
5959 WREG32(CP_INT_CNTL_RING0, tmp);
5962 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5963 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5964 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5965 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
6216 u32 wptr, tmp;
6232 tmp = RREG32(IH_RB_CNTL);
6233 tmp |= IH_WPTR_OVERFLOW_CLEAR;
6234 WREG32(IH_RB_CNTL, tmp);
7144 u32 max_lw, current_lw, tmp;
7149 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7150 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
7151 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
7154 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7155 if (tmp & LC_RENEGOTIATION_SUPPORT) {
7156 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
7157 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
7158 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
7159 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
7183 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7184 tmp |= LC_SET_QUIESCE;
7185 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7187 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7188 tmp |= LC_REDO_EQ;
7189 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7227 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7228 tmp &= ~LC_SET_QUIESCE;
7229 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);