Lines Matching defs:ring
3377 struct radeon_ring *ring = &rdev->ring[fence->ring];
3378 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3381 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3382 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3383 radeon_ring_write(ring, 0);
3384 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3385 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3389 radeon_ring_write(ring, 0xFFFFFFFF);
3390 radeon_ring_write(ring, 0);
3391 radeon_ring_write(ring, 10); /* poll interval */
3393 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3394 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3395 radeon_ring_write(ring, lower_32_bits(addr));
3396 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3397 radeon_ring_write(ring, fence->seq);
3398 radeon_ring_write(ring, 0);
3406 struct radeon_ring *ring = &rdev->ring[ib->ring];
3407 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3412 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3413 radeon_ring_write(ring, 0);
3418 if (ring->rptr_save_reg) {
3419 next_rptr = ring->wptr + 3 + 4 + 8;
3420 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3421 radeon_ring_write(ring, ((ring->rptr_save_reg -
3423 radeon_ring_write(ring, next_rptr);
3425 next_rptr = ring->wptr + 5 + 4 + 8;
3426 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3427 radeon_ring_write(ring, (1 << 8));
3428 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3429 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3430 radeon_ring_write(ring, next_rptr);
3436 radeon_ring_write(ring, header);
3437 radeon_ring_write(ring,
3442 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3443 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3447 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3448 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3449 radeon_ring_write(ring, vm_id);
3450 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3451 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3455 radeon_ring_write(ring, 0xFFFFFFFF);
3456 radeon_ring_write(ring, 0);
3457 radeon_ring_write(ring, 10); /* poll interval */
3473 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3474 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3475 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3563 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3566 r = radeon_ring_lock(rdev, ring, 7 + 4);
3568 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3572 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3573 radeon_ring_write(ring, 0x1);
3574 radeon_ring_write(ring, 0x0);
3575 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3576 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3577 radeon_ring_write(ring, 0);
3578 radeon_ring_write(ring, 0);
3581 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3582 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3583 radeon_ring_write(ring, 0xc000);
3584 radeon_ring_write(ring, 0xe000);
3585 radeon_ring_unlock_commit(rdev, ring, false);
3589 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3591 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3596 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3597 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3600 radeon_ring_write(ring, si_default_state[i]);
3602 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3603 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3606 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3607 radeon_ring_write(ring, 0);
3609 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3610 radeon_ring_write(ring, 0x00000316);
3611 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3612 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3614 radeon_ring_unlock_commit(rdev, ring, false);
3617 ring = &rdev->ring[i];
3618 r = radeon_ring_lock(rdev, ring, 2);
3620 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3625 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3626 radeon_ring_write(ring, 0);
3628 radeon_ring_unlock_commit(rdev, ring, false);
3636 struct radeon_ring *ring;
3639 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3640 radeon_ring_fini(rdev, ring);
3641 radeon_scratch_free(rdev, ring->rptr_save_reg);
3643 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3644 radeon_ring_fini(rdev, ring);
3645 radeon_scratch_free(rdev, ring->rptr_save_reg);
3647 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3648 radeon_ring_fini(rdev, ring);
3649 radeon_scratch_free(rdev, ring->rptr_save_reg);
3654 struct radeon_ring *ring;
3670 /* ring 0 - compute and gfx */
3671 /* Set ring buffer size */
3672 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3673 rb_bufsz = order_base_2(ring->ring_size / 8);
3680 /* Initialize the ring buffer's read and write pointers */
3682 ring->wptr = 0;
3683 WREG32(CP_RB0_WPTR, ring->wptr);
3699 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3702 /* Set ring buffer size */
3703 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3704 rb_bufsz = order_base_2(ring->ring_size / 8);
3711 /* Initialize the ring buffer's read and write pointers */
3713 ring->wptr = 0;
3714 WREG32(CP_RB1_WPTR, ring->wptr);
3723 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3726 /* Set ring buffer size */
3727 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3728 rb_bufsz = order_base_2(ring->ring_size / 8);
3735 /* Initialize the ring buffer's read and write pointers */
3737 ring->wptr = 0;
3738 WREG32(CP_RB2_WPTR, ring->wptr);
3747 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3751 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3752 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3753 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3754 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3756 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3757 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3758 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3761 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3763 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3765 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3767 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
4126 * @ring: radeon_ring structure holding ring information
4131 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4138 radeon_ring_lockup_update(rdev, ring);
4141 return radeon_ring_test_lockup(rdev, ring);
4764 switch (ib->ring) {
4773 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
5080 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5084 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5085 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5089 radeon_ring_write(ring,
5092 radeon_ring_write(ring,
5095 radeon_ring_write(ring, 0);
5096 radeon_ring_write(ring, pd_addr >> 12);
5099 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5100 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5102 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5103 radeon_ring_write(ring, 0);
5104 radeon_ring_write(ring, 0x1);
5107 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5108 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5110 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5111 radeon_ring_write(ring, 0);
5112 radeon_ring_write(ring, 1 << vm_id);
5115 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5116 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
5118 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5119 radeon_ring_write(ring, 0);
5120 radeon_ring_write(ring, 0); /* ref */
5121 radeon_ring_write(ring, 0); /* mask */
5122 radeon_ring_write(ring, 0x20); /* poll interval */
5125 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5126 radeon_ring_write(ring, 0x0);
5988 /* allocate ring */
6011 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
6225 /* When a ring buffer overflow happen start parsing interrupt
6229 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
6240 * Each IV ring entry is 128 bits:
6277 /* Order reading of wptr vs. reading of IH ring data */
6286 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
6287 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
6288 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
6483 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
6484 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
6507 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
6512 struct radeon_ring *ring;
6515 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
6518 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6519 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
6521 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
6550 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
6551 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
6552 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
6553 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
6586 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
6587 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
6592 struct radeon_ring *ring;
6595 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
6598 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
6599 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
6601 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
6604 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
6605 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
6607 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
6619 struct radeon_ring *ring;
6713 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6714 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
6719 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6720 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
6725 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6726 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
6731 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6732 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
6737 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6738 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
6834 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6895 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6896 ring->ring_obj = NULL;
6897 r600_ring_init(rdev, ring, 1024 * 1024);
6899 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6900 ring->ring_obj = NULL;
6901 r600_ring_init(rdev, ring, 1024 * 1024);
6903 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6904 ring->ring_obj = NULL;
6905 r600_ring_init(rdev, ring, 1024 * 1024);
6907 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6908 ring->ring_obj = NULL;
6909 r600_ring_init(rdev, ring, 64 * 1024);
6911 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6912 ring->ring_obj = NULL;
6913 r600_ring_init(rdev, ring, 64 * 1024);