Lines Matching refs:pi
56 struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
58 return pi;
63 struct evergreen_power_info *pi = rdev->pm.dpm.priv;
65 return pi;
71 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
80 if (!pi->boot_in_gen2) {
145 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
158 if (pi->mgcgtssm)
237 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
240 pi->soft_regs_start + reg_offset,
241 value, pi->sram_end);
248 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
251 pi->soft_regs_start + reg_offset,
252 value, pi->sram_end);
260 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
271 a_n = (int)state->medium.sclk * pi->lmp +
272 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp);
273 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) +
274 (int)state->medium.sclk * pi->lmp;
276 l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d);
277 r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d);
279 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk *
280 (R600_AH_DFLT - pi->rmp);
281 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) +
282 (int)state->high.sclk * pi->lhp;
284 l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d);
285 r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d);
288 a_t = CG_R(r[i] * pi->bsp / 200) | CG_L(l[i] * pi->bsp / 200);
292 a_t = CG_R(r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200) |
293 CG_L(l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200);
305 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
309 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
312 cpu_to_be32(pi->psp);
389 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
392 pi->clk_regs.rv770.mpll_ad_func_cntl;
394 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
396 pi->clk_regs.rv770.mpll_dq_func_cntl;
398 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
400 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
401 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
418 pi->mem_gddr5,
443 if (pi->mem_gddr5) {
446 pi->mem_gddr5,
487 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
490 pi->clk_regs.rv770.cg_spll_func_cntl;
492 pi->clk_regs.rv770.cg_spll_func_cntl_2;
494 pi->clk_regs.rv770.cg_spll_func_cntl_3;
496 pi->clk_regs.rv770.cg_spll_spread_spectrum;
498 pi->clk_regs.rv770.cg_spll_spread_spectrum_2;
537 if (pi->sclk_ss) {
568 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
571 if (!pi->voltage_control) {
577 for (i = 0; i < pi->valid_vddc_entries; i++) {
578 if (vddc <= pi->vddc_table[i].vddc) {
579 voltage->index = pi->vddc_table[i].vddc_index;
585 if (i == pi->valid_vddc_entries)
594 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
596 if (!pi->mvdd_control) {
602 if (mclk <= pi->mvdd_split_frequency) {
618 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
621 level->gen2PCIE = pi->pcie_gen2 ?
640 if (pi->mem_gddr5) {
641 if (pl->mclk <= pi->mclk_strobe_mode_threshold)
647 if (pl->mclk > pi->mclk_edc_enable_threshold)
742 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
756 STATE0(64 * high_clock / pi->boot_sclk) |
763 POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) |
782 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
785 if (pi->sclk_ss)
788 if (pi->mclk_ss) {
806 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
808 if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) {
810 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |
817 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
820 r600_calculate_u_and_p(pi->asi,
823 &pi->bsp,
824 &pi->bsu);
826 r600_calculate_u_and_p(pi->pasi,
829 &pi->pbsp,
830 &pi->pbsu);
832 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
833 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
835 WREG32(CG_BSP, pi->dsp);
889 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
891 WREG32(CG_FTV, pi->vrc);
901 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
907 ret = rv770_load_smc_ucode(rdev, pi->sram_end);
917 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
920 pi->clk_regs.rv770.mpll_ad_func_cntl;
922 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
924 pi->clk_regs.rv770.mpll_dq_func_cntl;
926 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
928 pi->clk_regs.rv770.cg_spll_func_cntl;
930 pi->clk_regs.rv770.cg_spll_func_cntl_2;
932 pi->clk_regs.rv770.cg_spll_func_cntl_3;
940 if (pi->acpi_vddc) {
941 rv770_populate_vddc_value(rdev, pi->acpi_vddc,
943 if (pi->pcie_gen2) {
944 if (pi->acpi_pcie_gen2)
950 if (pi->acpi_pcie_gen2)
955 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
1008 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1010 if ((pi->s0_vid_lower_smio_cntl & pi->mvdd_mask_low) ==
1011 (pi->mvdd_low_smio[MVDD_LOW_INDEX] & pi->mvdd_mask_low) ) {
1027 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1031 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1033 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1035 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1037 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1039 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1041 cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1044 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1046 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1052 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1054 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1056 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1058 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1060 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1079 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1081 if (pi->boot_in_gen2)
1091 if (pi->mem_gddr5) {
1092 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold)
1098 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)
1116 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1119 for (i = 0; i < pi->valid_vddc_entries; i++) {
1120 table->highSMIO[pi->vddc_table[i].vddc_index] =
1121 pi->vddc_table[i].high_smio;
1122 table->lowSMIO[pi->vddc_table[i].vddc_index] =
1123 cpu_to_be32(pi->vddc_table[i].low_smio);
1128 cpu_to_be32(pi->vddc_mask_low);
1131 ((i < pi->valid_vddc_entries) &&
1132 (pi->max_vddc_in_table >
1133 pi->vddc_table[i].vddc));
1137 pi->vddc_table[i].vddc_index;
1145 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1147 if (pi->mvdd_control) {
1149 cpu_to_be32(pi->mvdd_low_smio[MVDD_HIGH_INDEX]);
1151 cpu_to_be32(pi->mvdd_low_smio[MVDD_LOW_INDEX]);
1155 cpu_to_be32(pi->mvdd_mask_low);
1164 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1166 RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1171 pi->boot_sclk = boot_state->low.sclk;
1203 if (pi->mem_gddr5)
1225 pi->state_table_start,
1228 pi->sram_end);
1233 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1251 pi->vddc_table[i].vddc = (u16)(min + i * step);
1253 pi->vddc_table[i].vddc,
1256 pi->vddc_table[i].low_smio = gpio_pins & gpio_mask;
1257 pi->vddc_table[i].high_smio = 0;
1258 pi->vddc_mask_low = gpio_mask;
1260 if ((pi->vddc_table[i].low_smio !=
1261 pi->vddc_table[i - 1].low_smio ) ||
1262 (pi->vddc_table[i].high_smio !=
1263 pi->vddc_table[i - 1].high_smio))
1266 pi->vddc_table[i].vddc_index = vddc_index;
1269 pi->valid_vddc_entries = (u8)steps;
1284 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1290 pi->mvdd_mask_low = gpio_mask;
1291 pi->mvdd_low_smio[MVDD_HIGH_INDEX] =
1297 pi->mvdd_low_smio[MVDD_LOW_INDEX] =
1310 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1317 pi->mvdd_control = false;
1321 pi->mvdd_split_frequency =
1324 if (pi->mvdd_split_frequency == 0) {
1325 pi->mvdd_control = false;
1384 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1385 u16 address = pi->state_table_start +
1396 pi->sram_end);
1518 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1520 pi->clk_regs.rv770.cg_spll_func_cntl =
1522 pi->clk_regs.rv770.cg_spll_func_cntl_2 =
1524 pi->clk_regs.rv770.cg_spll_func_cntl_3 =
1526 pi->clk_regs.rv770.cg_spll_spread_spectrum =
1528 pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =
1530 pi->clk_regs.rv770.mpll_ad_func_cntl =
1532 pi->clk_regs.rv770.mpll_ad_func_cntl_2 =
1534 pi->clk_regs.rv770.mpll_dq_func_cntl =
1536 pi->clk_regs.rv770.mpll_dq_func_cntl_2 =
1538 pi->clk_regs.rv770.mclk_pwrmgt_cntl =
1540 pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
1555 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1557 pi->s0_vid_lower_smio_cntl =
1563 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1581 vid_smio_cntl = pi->s0_vid_lower_smio_cntl;
1591 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1598 pi->mem_gddr5 = true;
1600 pi->mem_gddr5 = false;
1606 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1613 pi->pcie_gen2 = true;
1615 pi->pcie_gen2 = false;
1617 if (pi->pcie_gen2) {
1619 pi->boot_in_gen2 = true;
1621 pi->boot_in_gen2 = false;
1623 pi->boot_in_gen2 = false;
1629 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1631 if (pi->gfx_clock_gating) {
1648 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1662 if (pi->gfx_clock_gating)
1671 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1675 pi->mclk_odt_threshold = 0;
1685 pi->mclk_odt_threshold = 30000;
1691 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1695 pi->max_vddc = 0;
1697 pi->max_vddc = vddc;
1747 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1753 if (pi->mclk_odt_threshold == 0)
1756 if (current_state->high.mclk <= pi->mclk_odt_threshold)
1759 if (new_state->high.mclk <= pi->mclk_odt_threshold)
1776 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1782 if (pi->mclk_odt_threshold == 0)
1785 if (current_state->high.mclk <= pi->mclk_odt_threshold)
1788 if (new_state->high.mclk <= pi->mclk_odt_threshold)
1803 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1805 if (pi->mclk_odt_threshold == 0)
1814 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1842 if (pi->thermal_protection)
1853 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1856 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1857 pi->active_auto_throttle_sources |= 1 << source;
1858 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1861 if (pi->active_auto_throttle_sources & (1 << source)) {
1862 pi->active_auto_throttle_sources &= ~(1 << source);
1863 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1895 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1899 if (pi->gfx_clock_gating)
1905 if (pi->voltage_control) {
1914 if (pi->dcodt)
1917 if (pi->mvdd_control) {
1930 if (pi->thermal_protection)
1943 if (pi->dynamic_pcie_gen2)
1965 if (pi->gfx_clock_gating)
1968 if (pi->mg_clock_gating)
2000 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2007 if (pi->thermal_protection)
2012 if (pi->dynamic_pcie_gen2)
2021 if (pi->gfx_clock_gating)
2024 if (pi->mg_clock_gating)
2038 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2060 if (pi->dcodt)
2072 if (pi->dcodt)
2082 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2086 if (pi->dcodt)
2089 if (pi->dcodt)
2096 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2101 if (pi->dcodt)
2177 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2220 if (pi->max_vddc)
2221 pl->vddc = pi->max_vddc;
2225 pi->acpi_vddc = pl->vddc;
2229 pi->acpi_pcie_gen2 = true;
2231 pi->acpi_pcie_gen2 = false;
2241 if (pi->min_vddc_in_table > pl->vddc)
2242 pi->min_vddc_in_table = pl->vddc;
2244 if (pi->max_vddc_in_table < pl->vddc)
2245 pi->max_vddc_in_table = pl->vddc;
2329 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2332 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2334 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2337 if (pi->sclk_ss || pi->mclk_ss)
2338 pi->dynamic_ss = true;
2340 pi->dynamic_ss = false;
2345 struct rv7xx_power_info *pi;
2349 pi = kzalloc(sizeof(struct rv7xx_power_info), GFP_KERNEL);
2350 if (pi == NULL)
2352 rdev->pm.dpm.priv = pi;
2356 pi->acpi_vddc = 0;
2357 pi->min_vddc_in_table = 0;
2358 pi->max_vddc_in_table = 0;
2376 pi->ref_div = dividers.ref_div + 1;
2378 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2380 pi->mclk_strobe_mode_threshold = 30000;
2381 pi->mclk_edc_enable_threshold = 30000;
2383 pi->rlp = RV770_RLP_DFLT;
2384 pi->rmp = RV770_RMP_DFLT;
2385 pi->lhp = RV770_LHP_DFLT;
2386 pi->lmp = RV770_LMP_DFLT;
2388 pi->voltage_control =
2391 pi->mvdd_control =
2396 pi->asi = RV770_ASI_DFLT;
2397 pi->pasi = RV770_HASI_DFLT;
2398 pi->vrc = RV770_VRC_DFLT;
2400 pi->power_gating = false;
2402 pi->gfx_clock_gating = true;
2404 pi->mg_clock_gating = true;
2405 pi->mgcgtssm = true;
2407 pi->dynamic_pcie_gen2 = true;
2410 pi->thermal_protection = true;
2412 pi->thermal_protection = false;
2414 pi->display_gap = true;
2417 pi->dcodt = true;
2419 pi->dcodt = false;
2421 pi->ulps = true;
2423 pi->mclk_stutter_mode_threshold = 0;
2425 pi->sram_end = SMC_RAM_END;
2426 pi->state_table_start = RV770_SMC_TABLE_ADDRESS;
2427 pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START;