Lines Matching refs:levels
289 smc_state->levels[i].aT = cpu_to_be32(a_t);
295 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
309 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
311 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
685 &smc_state->levels[0],
692 &smc_state->levels[1],
699 &smc_state->levels[2],
704 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
705 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
706 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
708 smc_state->levels[0].seqValue = rv770_get_seq_value(rdev,
710 smc_state->levels[1].seqValue = rv770_get_seq_value(rdev,
712 smc_state->levels[2].seqValue = rv770_get_seq_value(rdev,
942 &table->ACPIState.levels[0].vddc);
945 table->ACPIState.levels[0].gen2PCIE = 1;
947 table->ACPIState.levels[0].gen2PCIE = 0;
949 table->ACPIState.levels[0].gen2PCIE = 0;
951 table->ACPIState.levels[0].gen2XSP = 1;
953 table->ACPIState.levels[0].gen2XSP = 0;
956 &table->ACPIState.levels[0].vddc);
957 table->ACPIState.levels[0].gen2PCIE = 0;
981 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
982 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
983 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
984 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
986 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
987 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
989 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
991 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
992 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
993 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
995 table->ACPIState.levels[0].sclk.sclk_value = 0;
997 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
999 table->ACPIState.levels[1] = table->ACPIState.levels[0];
1000 table->ACPIState.levels[2] = table->ACPIState.levels[0];
1030 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1032 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1034 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1036 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1038 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1040 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1043 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1045 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1048 table->initialState.levels[0].mclk.mclk770.mclk_value =
1051 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1053 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1055 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1057 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1059 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1062 table->initialState.levels[0].sclk.sclk_value =
1065 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1067 table->initialState.levels[0].seqValue =
1072 &table->initialState.levels[0].vddc);
1074 &table->initialState.levels[0].mvdd);
1077 table->initialState.levels[0].aT = cpu_to_be32(a_t);
1079 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1082 table->initialState.levels[0].gen2PCIE = 1;
1084 table->initialState.levels[0].gen2PCIE = 0;
1086 table->initialState.levels[0].gen2XSP = 1;
1088 table->initialState.levels[0].gen2XSP = 0;
1093 table->initialState.levels[0].strobeMode =
1096 table->initialState.levels[0].strobeMode = 0;
1099 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1101 table->initialState.levels[0].mcFlags = 0;
1105 table->initialState.levels[1] = table->initialState.levels[0];
1106 table->initialState.levels[2] = table->initialState.levels[0];