Lines Matching defs:rdev
54 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev)
56 struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
61 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev)
63 struct evergreen_power_info *pi = rdev->pm.dpm.priv;
68 static void rv770_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
71 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
91 static void rv770_enable_l0s(struct radeon_device *rdev)
100 static void rv770_enable_l1(struct radeon_device *rdev)
112 static void rv770_enable_pll_sleep_in_l1(struct radeon_device *rdev)
129 static void rv770_gfx_clock_gating_enable(struct radeon_device *rdev,
142 static void rv770_mg_clock_gating_enable(struct radeon_device *rdev,
145 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
150 if (rdev->family == CHIP_RV770)
166 void rv770_restore_cgcg(struct radeon_device *rdev)
179 static void rv770_start_dpm(struct radeon_device *rdev)
188 void rv770_stop_dpm(struct radeon_device *rdev)
192 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
204 bool rv770_dpm_enabled(struct radeon_device *rdev)
212 void rv770_enable_thermal_protection(struct radeon_device *rdev,
221 void rv770_enable_acpi_pm(struct radeon_device *rdev)
226 u8 rv770_get_seq_value(struct radeon_device *rdev,
234 int rv770_read_smc_soft_register(struct radeon_device *rdev,
237 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
239 return rv770_read_smc_sram_dword(rdev,
245 int rv770_write_smc_soft_register(struct radeon_device *rdev,
248 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
250 return rv770_write_smc_sram_dword(rdev,
255 int rv770_populate_smc_t(struct radeon_device *rdev,
260 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
301 int rv770_populate_smc_sp(struct radeon_device *rdev,
305 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
370 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
385 static int rv770_populate_mclk_value(struct radeon_device *rdev,
389 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
403 u32 reference_clock = rdev->clock.mpll.reference_freq;
409 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
425 ibias = rv770_map_clkf_to_ibias(rdev, clkf);
449 ibias = rv770_map_clkf_to_ibias(rdev, clkf);
483 static int rv770_populate_sclk_value(struct radeon_device *rdev,
487 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
500 u32 reference_clock = rdev->clock.spll.reference_freq;
505 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
541 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
565 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
568 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
591 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
594 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
613 static int rv770_convert_power_level_to_smc(struct radeon_device *rdev,
618 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
627 if (rdev->family == CHIP_RV740)
628 ret = rv740_populate_sclk_value(rdev, pl->sclk,
630 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
631 ret = rv730_populate_sclk_value(rdev, pl->sclk,
634 ret = rv770_populate_sclk_value(rdev, pl->sclk,
639 if (rdev->family == CHIP_RV740) {
652 ret = rv740_populate_mclk_value(rdev, pl->sclk,
654 } else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
655 ret = rv730_populate_mclk_value(rdev, pl->sclk,
658 ret = rv770_populate_mclk_value(rdev, pl->sclk,
663 ret = rv770_populate_vddc_value(rdev, pl->vddc,
668 ret = rv770_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
673 static int rv770_convert_power_state_to_smc(struct radeon_device *rdev,
683 ret = rv770_convert_power_level_to_smc(rdev,
690 ret = rv770_convert_power_level_to_smc(rdev,
697 ret = rv770_convert_power_level_to_smc(rdev,
708 smc_state->levels[0].seqValue = rv770_get_seq_value(rdev,
710 smc_state->levels[1].seqValue = rv770_get_seq_value(rdev,
712 smc_state->levels[2].seqValue = rv770_get_seq_value(rdev,
715 rv770_populate_smc_sp(rdev, radeon_state, smc_state);
717 return rv770_populate_smc_t(rdev, radeon_state, smc_state);
721 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
738 static void rv770_program_memory_timing_parameters(struct radeon_device *rdev,
742 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
752 radeon_atom_set_engine_dram_timings(rdev, high_clock,
763 POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) |
764 POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
765 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
766 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk));
770 void rv770_enable_backbias(struct radeon_device *rdev,
779 static void rv770_enable_spread_spectrum(struct radeon_device *rdev,
782 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
789 if (rdev->family == CHIP_RV740)
790 rv740_enable_mclk_spread_spectrum(rdev, true);
799 if (rdev->family == CHIP_RV740)
800 rv740_enable_mclk_spread_spectrum(rdev, false);
804 static void rv770_program_mpll_timing_parameters(struct radeon_device *rdev)
806 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
808 if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) {
815 void rv770_setup_bsp(struct radeon_device *rdev)
817 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
818 u32 xclk = radeon_get_xclk(rdev);
839 void rv770_program_git(struct radeon_device *rdev)
844 void rv770_program_tp(struct radeon_device *rdev)
862 void rv770_program_tpp(struct radeon_device *rdev)
867 void rv770_program_sstp(struct radeon_device *rdev)
872 void rv770_program_engine_speed_parameters(struct radeon_device *rdev)
877 static void rv770_enable_display_gap(struct radeon_device *rdev)
887 void rv770_program_vc(struct radeon_device *rdev)
889 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
894 void rv770_clear_vc(struct radeon_device *rdev)
899 int rv770_upload_firmware(struct radeon_device *rdev)
901 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
904 rv770_reset_smc(rdev);
905 rv770_stop_smc_clock(rdev);
907 ret = rv770_load_smc_ucode(rdev, pi->sram_end);
914 static int rv770_populate_smc_acpi_state(struct radeon_device *rdev,
917 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
941 rv770_populate_vddc_value(rdev, pi->acpi_vddc,
955 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
997 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1005 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
1008 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1022 static int rv770_populate_smc_initial_state(struct radeon_device *rdev,
1027 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1068 rv770_get_seq_value(rdev, &initial_state->low);
1070 rv770_populate_vddc_value(rdev,
1073 rv770_populate_initial_mvdd_value(rdev,
1090 if (rdev->family == CHIP_RV740) {
1113 static int rv770_populate_smc_vddc_table(struct radeon_device *rdev,
1116 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1142 static int rv770_populate_smc_mvdd_table(struct radeon_device *rdev,
1145 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1161 static int rv770_init_smc_table(struct radeon_device *rdev,
1164 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1173 rv770_populate_smc_vddc_table(rdev, table);
1174 rv770_populate_smc_mvdd_table(rdev, table);
1176 switch (rdev->pm.int_thermal_type) {
1190 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) {
1193 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT)
1196 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT)
1200 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1206 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1207 ret = rv730_populate_smc_initial_state(rdev, radeon_boot_state, table);
1209 ret = rv770_populate_smc_initial_state(rdev, radeon_boot_state, table);
1213 if (rdev->family == CHIP_RV740)
1214 ret = rv740_populate_smc_acpi_state(rdev, table);
1215 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1216 ret = rv730_populate_smc_acpi_state(rdev, table);
1218 ret = rv770_populate_smc_acpi_state(rdev, table);
1224 return rv770_copy_bytes_to_smc(rdev,
1231 static int rv770_construct_vddc_table(struct radeon_device *rdev)
1233 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1239 radeon_atom_get_min_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &min);
1240 radeon_atom_get_max_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &max);
1241 radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &step);
1252 radeon_atom_get_voltage_gpio_settings(rdev,
1282 static int rv770_get_mvdd_pin_configuration(struct radeon_device *rdev)
1284 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1287 radeon_atom_get_voltage_gpio_settings(rdev,
1294 radeon_atom_get_voltage_gpio_settings(rdev,
1303 u8 rv770_get_memory_module_index(struct radeon_device *rdev)
1308 static int rv770_get_mvdd_configuration(struct radeon_device *rdev)
1310 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1314 memory_module_index = rv770_get_memory_module_index(rdev);
1316 if (radeon_atom_get_memory_info(rdev, memory_module_index, &memory_info)) {
1329 return rv770_get_mvdd_pin_configuration(rdev);
1332 void rv770_enable_voltage_control(struct radeon_device *rdev,
1341 static void rv770_program_display_gap(struct radeon_device *rdev)
1346 if (rdev->pm.dpm.new_active_crtcs & 1) {
1349 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1359 static void rv770_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1362 rv770_enable_bif_dynamic_pcie_gen2(rdev, enable);
1370 static void r7xx_program_memory_timing_parameters(struct radeon_device *rdev,
1373 if ((rdev->family == CHIP_RV730) ||
1374 (rdev->family == CHIP_RV710) ||
1375 (rdev->family == CHIP_RV740))
1376 rv730_program_memory_timing_parameters(rdev, radeon_new_state);
1378 rv770_program_memory_timing_parameters(rdev, radeon_new_state);
1381 static int rv770_upload_sw_state(struct radeon_device *rdev,
1384 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1390 ret = rv770_convert_power_state_to_smc(rdev, radeon_new_state, &state);
1394 return rv770_copy_bytes_to_smc(rdev, address, (const u8 *)&state,
1399 int rv770_halt_smc(struct radeon_device *rdev)
1401 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
1404 if (rv770_wait_for_smc_inactive(rdev) != PPSMC_Result_OK)
1410 int rv770_resume_smc(struct radeon_device *rdev)
1412 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_Resume) != PPSMC_Result_OK)
1417 int rv770_set_sw_state(struct radeon_device *rdev)
1419 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
1424 int rv770_set_boot_state(struct radeon_device *rdev)
1426 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) != PPSMC_Result_OK)
1431 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
1445 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1448 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
1462 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1465 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1467 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_NoForcedLevel)) != PPSMC_Result_OK)
1470 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_TwoLevelsDisabled)) != PPSMC_Result_OK)
1476 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
1482 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ZeroLevelsDisabled) != PPSMC_Result_OK)
1486 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1490 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1495 if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
1498 rdev->pm.dpm.forced_level = level;
1503 void r7xx_start_smc(struct radeon_device *rdev)
1505 rv770_start_smc(rdev);
1506 rv770_start_smc_clock(rdev);
1510 void r7xx_stop_smc(struct radeon_device *rdev)
1512 rv770_reset_smc(rdev);
1513 rv770_stop_smc_clock(rdev);
1516 static void rv770_read_clock_registers(struct radeon_device *rdev)
1518 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1543 static void r7xx_read_clock_registers(struct radeon_device *rdev)
1545 if (rdev->family == CHIP_RV740)
1546 rv740_read_clock_registers(rdev);
1547 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1548 rv730_read_clock_registers(rdev);
1550 rv770_read_clock_registers(rdev);
1553 void rv770_read_voltage_smio_registers(struct radeon_device *rdev)
1555 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1561 void rv770_reset_smio_status(struct radeon_device *rdev)
1563 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1589 void rv770_get_memory_type(struct radeon_device *rdev)
1591 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1604 void rv770_get_pcie_gen2_status(struct radeon_device *rdev)
1606 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1627 static int rv770_enter_ulp_state(struct radeon_device *rdev)
1629 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1646 static int rv770_exit_ulp_state(struct radeon_device *rdev)
1648 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1656 for (i = 0; i < rdev->usec_timeout; i++) {
1669 static void rv770_get_mclk_odt_threshold(struct radeon_device *rdev)
1671 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1677 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) {
1678 memory_module_index = rv770_get_memory_module_index(rdev);
1680 if (radeon_atom_get_memory_info(rdev, memory_module_index, &memory_info))
1689 void rv770_get_max_vddc(struct radeon_device *rdev)
1691 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1694 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc))
1700 void rv770_program_response_times(struct radeon_device *rdev)
1707 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1708 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1719 reference_clock = radeon_get_xclk(rdev);
1726 rv770_write_smc_soft_register(rdev,
1728 rv770_write_smc_soft_register(rdev,
1730 rv770_write_smc_soft_register(rdev,
1732 rv770_write_smc_soft_register(rdev,
1737 rv770_write_smc_soft_register(rdev,
1743 static void rv770_program_dcodt_before_state_switch(struct radeon_device *rdev,
1747 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1768 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1769 rv730_program_dcodt(rdev, new_use_dc);
1772 static void rv770_program_dcodt_after_state_switch(struct radeon_device *rdev,
1776 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1797 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1798 rv730_program_dcodt(rdev, new_use_dc);
1801 static void rv770_retrieve_odt_values(struct radeon_device *rdev)
1803 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1808 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1809 rv730_get_odt_values(rdev);
1812 static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1814 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1849 void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
1853 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1858 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1863 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1868 static int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
1887 rdev->pm.dpm.thermal.min_temp = low_temp;
1888 rdev->pm.dpm.thermal.max_temp = high_temp;
1893 int rv770_dpm_enable(struct radeon_device *rdev)
1895 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1896 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1900 rv770_restore_cgcg(rdev);
1902 if (rv770_dpm_enabled(rdev))
1906 rv770_enable_voltage_control(rdev, true);
1907 ret = rv770_construct_vddc_table(rdev);
1915 rv770_retrieve_odt_values(rdev);
1918 ret = rv770_get_mvdd_configuration(rdev);
1925 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1926 rv770_enable_backbias(rdev, true);
1928 rv770_enable_spread_spectrum(rdev, true);
1931 rv770_enable_thermal_protection(rdev, true);
1933 rv770_program_mpll_timing_parameters(rdev);
1934 rv770_setup_bsp(rdev);
1935 rv770_program_git(rdev);
1936 rv770_program_tp(rdev);
1937 rv770_program_tpp(rdev);
1938 rv770_program_sstp(rdev);
1939 rv770_program_engine_speed_parameters(rdev);
1940 rv770_enable_display_gap(rdev);
1941 rv770_program_vc(rdev);
1944 rv770_enable_dynamic_pcie_gen2(rdev, true);
1946 ret = rv770_upload_firmware(rdev);
1951 ret = rv770_init_smc_table(rdev, boot_ps);
1957 rv770_program_response_times(rdev);
1958 r7xx_start_smc(rdev);
1960 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1961 rv730_start_dpm(rdev);
1963 rv770_start_dpm(rdev);
1966 rv770_gfx_clock_gating_enable(rdev, true);
1969 rv770_mg_clock_gating_enable(rdev, true);
1971 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1976 int rv770_dpm_late_enable(struct radeon_device *rdev)
1980 if (rdev->irq.installed &&
1981 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1984 ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1987 rdev->irq.dpm_thermal = true;
1988 radeon_irq_set(rdev);
1989 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
1998 void rv770_dpm_disable(struct radeon_device *rdev)
2000 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2002 if (!rv770_dpm_enabled(rdev))
2005 rv770_clear_vc(rdev);
2008 rv770_enable_thermal_protection(rdev, false);
2010 rv770_enable_spread_spectrum(rdev, false);
2013 rv770_enable_dynamic_pcie_gen2(rdev, false);
2015 if (rdev->irq.installed &&
2016 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2017 rdev->irq.dpm_thermal = false;
2018 radeon_irq_set(rdev);
2022 rv770_gfx_clock_gating_enable(rdev, false);
2025 rv770_mg_clock_gating_enable(rdev, false);
2027 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
2028 rv730_stop_dpm(rdev);
2030 rv770_stop_dpm(rdev);
2032 r7xx_stop_smc(rdev);
2033 rv770_reset_smio_status(rdev);
2036 int rv770_dpm_set_power_state(struct radeon_device *rdev)
2038 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2039 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
2040 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
2043 ret = rv770_restrict_performance_levels_before_switch(rdev);
2048 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
2049 ret = rv770_halt_smc(rdev);
2054 ret = rv770_upload_sw_state(rdev, new_ps);
2059 r7xx_program_memory_timing_parameters(rdev, new_ps);
2061 rv770_program_dcodt_before_state_switch(rdev, new_ps, old_ps);
2062 ret = rv770_resume_smc(rdev);
2067 ret = rv770_set_sw_state(rdev);
2073 rv770_program_dcodt_after_state_switch(rdev, new_ps, old_ps);
2074 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2080 void rv770_dpm_reset_asic(struct radeon_device *rdev)
2082 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2083 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2085 rv770_restrict_performance_levels_before_switch(rdev);
2087 rv770_program_dcodt_before_state_switch(rdev, boot_ps, boot_ps);
2088 rv770_set_boot_state(rdev);
2090 rv770_program_dcodt_after_state_switch(rdev, boot_ps, boot_ps);
2094 void rv770_dpm_setup_asic(struct radeon_device *rdev)
2096 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2098 r7xx_read_clock_registers(rdev);
2099 rv770_read_voltage_smio_registers(rdev);
2100 rv770_get_memory_type(rdev);
2102 rv770_get_mclk_odt_threshold(rdev);
2103 rv770_get_pcie_gen2_status(rdev);
2105 rv770_enable_acpi_pm(rdev);
2108 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
2109 rv770_enable_l0s(rdev);
2110 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
2111 rv770_enable_l1(rdev);
2112 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
2113 rv770_enable_pll_sleep_in_l1(rdev);
2117 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev)
2119 rv770_program_display_gap(rdev);
2143 static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
2168 rdev->pm.dpm.boot_ps = rps;
2170 rdev->pm.dpm.uvd_ps = rps;
2173 static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev,
2177 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2178 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2196 if (rdev->family >= CHIP_CEDAR) {
2226 if (rdev->family >= CHIP_CEDAR)
2235 if (rdev->family >= CHIP_BARTS) {
2250 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2251 pl->mclk = rdev->clock.default_mclk;
2252 pl->sclk = rdev->clock.default_sclk;
2259 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
2260 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
2266 int rv7xx_parse_power_table(struct radeon_device *rdev)
2268 struct radeon_mode_info *mode_info = &rdev->mode_info;
2284 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
2287 if (!rdev->pm.dpm.ps)
2304 kfree(rdev->pm.dpm.ps);
2307 rdev->pm.dpm.ps[i].ps_priv = ps;
2308 rv7xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2317 rv7xx_parse_pplib_clock_info(rdev,
2318 &rdev->pm.dpm.ps[i], j,
2323 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
2327 void rv770_get_engine_memory_ss(struct radeon_device *rdev)
2329 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2332 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2334 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2343 int rv770_dpm_init(struct radeon_device *rdev)
2352 rdev->pm.dpm.priv = pi;
2354 rv770_get_max_vddc(rdev);
2360 ret = r600_get_platform_caps(rdev);
2364 ret = rv7xx_parse_power_table(rdev);
2368 if (rdev->pm.dpm.voltage_response_time == 0)
2369 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2370 if (rdev->pm.dpm.backbias_response_time == 0)
2371 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2373 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2389 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2392 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2394 rv770_get_engine_memory_ss(rdev);
2409 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2416 if (rdev->flags & RADEON_IS_MOBILITY)
2432 void rv770_dpm_print_power_state(struct radeon_device *rdev,
2441 if (rdev->family >= CHIP_CEDAR) {
2462 r600_dpm_print_ps_status(rdev, rps);
2465 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2468 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2485 if (rdev->family >= CHIP_CEDAR) {
2495 u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev)
2497 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2517 u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev)
2519 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2539 void rv770_dpm_fini(struct radeon_device *rdev)
2543 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2544 kfree(rdev->pm.dpm.ps[i].ps_priv);
2546 kfree(rdev->pm.dpm.ps);
2547 kfree(rdev->pm.dpm.priv);
2550 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low)
2552 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
2560 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)
2562 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
2570 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev)
2572 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2577 if ((rdev->family == CHIP_RV770) &&
2578 !(rdev->flags & RADEON_IS_MOBILITY))