Lines Matching refs:levels
246 &table->ACPIState.levels[0].vddc);
247 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
249 table->ACPIState.levels[0].gen2XSP =
253 &table->ACPIState.levels[0].vddc);
254 table->ACPIState.levels[0].gen2PCIE = 0;
296 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
297 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
298 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
299 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
300 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
302 table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
305 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
306 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
308 table->ACPIState.levels[0].sclk.sclk_value = 0;
310 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
312 table->ACPIState.levels[1] = table->ACPIState.levels[0];
313 table->ACPIState.levels[2] = table->ACPIState.levels[0];
326 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
328 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
330 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
332 table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
334 table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
336 table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
338 table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
341 table->initialState.levels[0].mclk.mclk730.mclk_value =
344 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
346 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
348 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
350 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
352 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
355 table->initialState.levels[0].sclk.sclk_value =
358 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
360 table->initialState.levels[0].seqValue =
365 &table->initialState.levels[0].vddc);
367 &table->initialState.levels[0].mvdd);
371 table->initialState.levels[0].aT = cpu_to_be32(a_t);
373 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
376 table->initialState.levels[0].gen2PCIE = 1;
378 table->initialState.levels[0].gen2PCIE = 0;
380 table->initialState.levels[0].gen2XSP = 1;
382 table->initialState.levels[0].gen2XSP = 0;
384 table->initialState.levels[1] = table->initialState.levels[0];
385 table->initialState.levels[2] = table->initialState.levels[0];