Lines Matching refs:pi
45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
47 return pi;
162 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
167 pi->spll_ref_div,
183 fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
184 pi->fb_div_scale;
187 pi->spll_ref_div - 1);
436 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
438 pi->hw.sclks[R600_POWER_LEVEL_LOW] =
440 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =
442 pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
445 pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
446 pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;
447 pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
453 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
455 pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =
457 pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
459 pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =
461 pi->hw.mclks[R600_POWER_LEVEL_LOW] =
464 pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
467 pi->hw.medium_mclk_index =
468 pi->hw.high_mclk_index;
470 pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;
474 pi->hw.low_mclk_index =
475 pi->hw.medium_mclk_index;
477 pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
483 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
485 pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
486 pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
487 pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
488 pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
490 pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =
492 pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
494 pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
496 pi->hw.backbias[R600_POWER_LEVEL_LOW] =
499 pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
501 pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =
503 pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
506 pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
511 pi->hw.medium_vddc_index =
512 pi->hw.high_vddc_index;
514 pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;
519 pi->hw.low_vddc_index =
520 pi->hw.medium_vddc_index;
522 pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
552 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
559 if (clock && pi->sclk_ss) {
562 pi->fb_div_scale);
570 pi->fb_div_scale);
585 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
588 pi->hw.sclks[R600_POWER_LEVEL_HIGH],
592 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
620 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
624 if (pi->hw.mclks[i])
626 pi->hw.mclks[i]);
636 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
643 pi->fb_div_scale);
654 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
662 if (pi->mclk_ss) {
664 pi->hw.mclks[pi->hw.high_mclk_index],
670 pi->hw.mclks[pi->hw.medium_mclk_index],
676 pi->hw.mclks[pi->hw.low_mclk_index],
688 pi->fb_div_scale);
720 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
725 pi->hw.vddc[i]);
731 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
733 if (pi->hw.backbias[1])
738 if (pi->hw.backbias[2])
746 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
749 pi->hw.sclks[R600_POWER_LEVEL_LOW],
755 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
757 if (pi->hw.mclks[0])
759 pi->hw.mclks[0]);
764 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
767 pi->hw.vddc[0]);
773 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
775 if (pi->hw.backbias[0])
796 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
801 if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
802 (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
803 high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
806 pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
810 sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |
811 STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |
812 STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
813 STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
818 pi->hw.sclks[R600_POWER_LEVEL_LOW])) |
820 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
822 pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
824 pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
830 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
833 pi->mpll_ref_div);
839 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
844 &pi->bsp,
845 &pi->bsu);
847 r600_set_bsp(rdev, pi->bsu, pi->bsp);
852 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
855 (pi->hw.rp[0] * pi->bsp) / 200,
856 (pi->hw.rp[1] * pi->bsp) / 200,
857 (pi->hw.lp[2] * pi->bsp) / 200,
858 (pi->hw.lp[1] * pi->bsp) / 200);
939 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
948 pi->hw.vddc[i],
1021 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1023 pi->hw.lp[0] = 0;
1024 pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]
1032 &pi->hw.lp[1],
1033 &pi->hw.rp[0]);
1040 &pi->hw.lp[2],
1041 &pi->hw.rp[1]);
1058 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1061 if (pi->voltage_control)
1071 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1074 if (pi->voltage_control)
1082 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1085 pi->hw.low_vddc_index);
1087 pi->hw.low_mclk_index);
1089 pi->hw.low_sclk_index);
1093 pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1098 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1108 pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1114 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1117 pi->hw.medium_vddc_index);
1119 pi->hw.medium_mclk_index);
1121 pi->hw.medium_sclk_index);
1125 pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
1130 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1134 pi->hw.mclks[pi->hw.low_mclk_index]);
1141 pi->hw.medium_sclk_index);
1149 pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1154 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1157 pi->hw.high_vddc_index);
1159 pi->hw.high_mclk_index);
1161 pi->hw.high_sclk_index);
1167 pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
1336 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1338 if ((pi->restricted_levels < 1) ||
1339 (pi->restricted_levels == 3))
1345 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1347 if (pi->restricted_levels < 2)
1353 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1381 if (pi->thermal_protection)
1392 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1395 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1396 pi->active_auto_throttle_sources |= 1 << source;
1397 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1400 if (pi->active_auto_throttle_sources & (1 << source)) {
1401 pi->active_auto_throttle_sources &= ~(1 << source);
1402 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1411 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1413 if (pi->active_auto_throttle_sources)
1423 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1428 0, &pi->hw.medium_sclk_index);
1435 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1437 pi->hw.low_sclk_index = 0;
1445 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1448 pi->hw.medium_sclk_index);
1455 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1457 pi->hw.low_sclk_index = 0;
1463 &pi->hw.medium_sclk_index);
1467 pi->hw.medium_sclk_index,
1468 &pi->hw.high_sclk_index);
1547 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1556 if (pi->dynamic_ss)
1571 if (pi->display_gap == false)
1578 if (pi->voltage_control)
1600 if (pi->voltage_control)
1603 if (pi->dynamic_pcie_gen2)
1606 if (pi->gfx_clock_gating)
1614 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1626 if (pi->thermal_protection)
1638 if (pi->voltage_control)
1641 if (pi->dynamic_pcie_gen2)
1650 if (pi->gfx_clock_gating)
1658 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1663 pi->restricted_levels = 0;
1671 if (pi->thermal_protection)
1681 if (pi->voltage_control) {
1690 if (pi->dynamic_pcie_gen2)
1693 if (pi->voltage_control)
1699 if (pi->voltage_control) {
1719 if (pi->voltage_control) {
1731 if (pi->dynamic_pcie_gen2)
1744 if (pi->thermal_protection)
1936 struct rv6xx_power_info *pi;
1939 pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
1940 if (pi == NULL)
1942 rdev->pm.dpm.priv = pi;
1960 pi->spll_ref_div = dividers.ref_div + 1;
1962 pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1967 pi->mpll_ref_div = dividers.ref_div + 1;
1969 pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1972 pi->fb_div_scale = 1;
1974 pi->fb_div_scale = 0;
1976 pi->voltage_control =
1979 pi->gfx_clock_gating = true;
1981 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1983 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1987 pi->sclk_ss = false;
1989 if (pi->sclk_ss || pi->mclk_ss)
1990 pi->dynamic_ss = true;
1992 pi->dynamic_ss = false;
1994 pi->dynamic_pcie_gen2 = true;
1996 if (pi->gfx_clock_gating &&
1998 pi->thermal_protection = true;
2000 pi->thermal_protection = false;
2002 pi->display_gap = true;
2133 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2136 pi->restricted_levels = 3;
2138 pi->restricted_levels = 2;
2140 pi->restricted_levels = 0;
2151 if (pi->restricted_levels == 3)