Lines Matching defs:index
297 u32 clock, u32 index)
302 rv6xx_output_stepping(rdev, index, &step);
315 u32 index, u32 clk_s)
317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
322 u32 index, u32 clk_v)
324 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
329 u32 index, bool enable)
332 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
335 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
370 u32 index, bool enable)
373 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
376 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
380 u32 index, u32 divider)
382 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
387 u32 index, u32 divider)
389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
394 u32 index, u32 divider)
396 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
1817 struct radeon_ps *rps, int index,
1825 switch (index) {
1880 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1885 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,